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subi Sto, Sto, 4 bne Stl SO A 2. You are tasked with designing a CPU with 40-bit wordsize. You are using a RISC instruction

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subi Sto, Sto, 4 bne Stl SO A 2. You are tasked with designing a CPU with 40-bit wordsize. You are using a RISC instruction set, similar to MIPS, with about 300 instruction codes. You will need at least R-format (3 register and instruction code) and I-format (2 register, a 20 bit data field and instruction code). Draw a diagram of fields in each 40 bit instruction format, label each field with its function and size. How many registers do you have? Are the registers all usable in every instruction position (general purpose, like MIPS), or are some registers special purpose

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