Subject - Computer Organization and Architecture [ Theory ]

///////// It's my 3rd-time post for this questions answer. if you don't have enough knowledge for solving this answer, please skip it.

Hi Experts! Would you please try to solve this as soon as possible with 100 % Accuracy? If possible, please do it.

You have to follow some instructions which I mentioned below. If you don't follow my instructions, please skip my questions.

You have to answer only #1 . I repeated, don't do other numbers.

Instructions are given,

• You need to show detailed calculations, as required.
• You need to provide clear diagrams, as required. All diagrams should be clearly drawn
• I added sample design for you .

CYCLE OPERATIONS Content of A Content of a Q Comments, if any Content of M Initialization 0000 1010 0 Initial Value Cycle-1 Q.Q., = 00 0000 0101 o 2,9 = 10 Cycle-2 0 1001 1100 0101 1010 QQ, - 10 9Q, = 01 1 Cycle-3 Arithmetic Shift right (AQQ) A= A-M Shift right (AQQ.,) A=A+M Shift right (AQQ, A=A-M Shift right (AQQ) 1 0011 0001 1010 1101 29, = 01 2,9 = 10 0111 lo Cycle-4 0 1010 1101 1101 0110 1 2.Q., = 10 99,= 01 Product is in: AQ pair: 11010110 in 2's complement since MSB is 1, to get magnitude, take 2's complement of AQ: 00101001 + 1 = 00101010 = 42 Answer: - 42 M.-1 M. n-bit adder control logic AR-1 Q2-1 Qe 1. 2. 3. Use the Booth algorithm to multiply -5 by +7. Draw the schematic of hardware and show the contents of each section after each cycle/step. A computer system contains a main memory of 32KB. It also has a 1KB cache divided into two-lines/set with 8Bytes per line. Assume that the cache is initially empty. The processor fetches words from locations 1024, 1025, 1026.......1072. and then 2048, 2049, 2050, .... 2096 in that order. It then repeats this fetch sequence two more times. Calculate the Hit ratio and show the state of cache at the end. Assume an LRU is used as replacement algorithm. Estimate the improvement resulting from the use of the cache, if the cache is 20 times faster than RAM. Just comment on relative Hit ratios and Execution times if Fully Associative and Direct Mapping are used here. Consider the following assembly code: Instruction Description LD R1, 45(R2) Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2 ADD R7, R1, R5 Add contents of R1 and R5 and store to R7 XOR R2, R7, R7 Logical Ex-OR between contents of R7 with R7 and store result in R2 BEZ R2, Target Jump to Target if R2 is Zero LD R3, 50(R4) Read data from memory and store in R3. Memory address is calculated by adding 50 to the content of R4 LD R5, 45(RO) Read data from memory and store in R5. Memory address is calculated by adding 45 to the content of R6 ADD R10, R5, R3 Add contents of R5 to R3 and store in R10 Target: AND R2, R3, R5 Logical AND between contents of R3 & R5. Store result to R2 ADD R10, R8, R2 Add contents of R2 and R8 and store to R10 END Use five-stage pipeline containing Fetch, Decode, Memory read, Execute, Write-back units, show the execution of above instructions. Data dependencies and control hazards, if detected must be resolved by delaying the pipeline as required. Assume that a multi-port RAM is used with the CPU running at 1GHz and each section requires 3 clock cycles. Calculate the execution time