Submission Instructions:

1. Please submit your work directly in TRACS (using the TRACS editor) or as a text/MS- word/PDF attachment by the due date/time.

2. Please use only zip for compression.

3. Please write your name in the assignment header and as a part of the file name of any file attached

4. Assume that $rs, $rt, and $rd are 12, 13, and 14 respecively.

5. Assume that each of the change of flow instructions is in address 0x88888888

6. and that the label is in address 0x88888844

Assignment Instructions:

1) Consider the instruction slt, which has the format: slt $rd, $rs, $rt. a. The instruction sets $rd to 1 if and only if $ < $. Otherwise it sets $rd to 0.

i. Provide an informal RTL (register transfer language) describing the instruction semantics

ii. Explain the way that the instruction is mapped into Figure 4.38 from the book by Patterson (enclosed and available on TRACS). The explanation should include the input, output, and role of each CPU unit during the IF, ID, Exe, Mem, and WB cycles of the instruction.

2) Consider the instruction slti, which has the format: slti $rt, $rs, constant.

a. The instruction sets $rt to 1 if and only if $ < . Otherwise it sets $rt to 0.

i. Provide an informal RTL (register transfer language) describing the instruction semantics

ii. Explain the way that the instruction is mapped into Figure 4.38 from the book by Patterson (enclosed and available on TRACS). The explanation should include the input, output, and role of each CPU unit during the Exe, Mem, and WB cycles of the instruction.

3) Consider the pseudo instruction b, which has the format: b label. The instructionperforms an un-conditional branch relative to PC to the label specified in the instruction. Since this is a pseudo instruction, the assembler first convert it into a real instruction usingbeq.

i. Provide an informal RTL (register transfer language) describing the instruction semantics

ii. Explain the way that the instruction is mapped into Figure 4.38 from the book by Patterson (enclosed and available on TRACS). The explanation should include the input, output, and role of each CPU unit during the Exe, Mem, and WB cycles of the instruction.

4) Consider the instruction lw which has the format: lw $rt, offset($rs). The instructionloads the contents the memory address pointed to by $rs+offset into the register $rt.

i. Provide an informal RTL (register transfer language) describing the instruction semantics

ii. Explain the way that the instruction is mapped into Figure 4.38 from the book by Patterson (enclosed and available on TRACS). The explanation should include the input, output, and role of each CPU unit during the Exe, Mem, and WB cycles of the instruction.

5) Consider the instruction jal, which has the format: jal label.

a. The instruction can be used to implement a function call.

i. Provide an informal RTL (register transfer language) describing the instruction semantics

ii. Explain the way that the instruction should be mapped into a modified version of Figure 4.38 from the book by Patterson (enclosed and available on TRACS). The explanation should include the input, output, and role of each CPU unit during the Exe, Mem, and WB cycles of the instruction.

Free PDF links for Patterson book (Figure 4.38 on page 293):

http://ac.aua.am/arm/public/2017-spring-computer-organization/textbooks/ComputerOrganizationAndDesign5thEdition2014.pdf

https://universalflowuniversity.com/Books/Computer%20Programming/Computers%2C%20Architecture%20and%20Design/Computer%20Organization%20and%20Design_%20The%20Hardware-Software%20Interface%205th%20Edition.pdf

http://bank.engzenon.com/download/530a01e8-0b30-4341-8c37-64fbc0e8c6f8/Computer_Organization_and_Design_By_David_Patterson_5th_ed.pdf