Supplemental Problem (40): For both parts of the problem we examine the dependencies of the following code sequence: lw addi add lw add $2, 0($3) $4, $2, 50 $3, $2, $4 $2,4($3) $4, $3, $4 Assumption we are using the classic 5-stage pipeline and that the registers can Write/Read in the same clock cycle. S.1 Draw a multi-cycle timing diagram (similar to Fig 4.53 and slide 81) to show the execution through the pipeline. Show stalls where appropriate. For this case S.2 Draw a multi-cycle timing diagram (similar to Fig 4.53 and slide 81) to show the execution through the pipeline. Show stalls and any forwarding where appropriate. For this case full forwarding is implemented