Question
Suppose registers R0 and R1 already hold a single 64-bit quantity with the most significant 32 bits in R0 and the least significant 32 bits
Suppose registers R0 and R1 already hold a single 64-bit quantity with the most significant 32 bits in R0 and the least significant 32 bits in R1. Give a minimum-length sequence of ARM Cortex-M3 instructions that would be required to implement:
A 64-bit logical right shift by 4-bit positions?
A 64-bit arithmetic right shift by 4-bit positions?
A 64-bit right rotate (not including the carry flag) by 2-bit positions?
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System Dynamics
Authors: William Palm III
3rd edition
73398063, 978-0073398068
