Question
Suppose we add the multiply and divide instructions. The operation times are as follows: Instruction memory access time = 190 ps, Data memory access time
Suppose we add the multiply and divide instructions. The operation times are as follows:
Instruction memory access time = 190 ps, Data memory access time = 190 ps,
Register file read access time = 150 ps, Register file write access = 150 ps
ALU delay for basic instructions = 190 ps, ALU delay for multiply or divide = 550 ps
Ignore the other delays in the multiplexers, control unit, sign-extension, etc.
Assume the following instruction mix: 30% ALU, 15% multiply & divide, 20% load, 10% store, 15% branch, and 10% jump.
What is the total delay for each instruction class and the clock cycle for the single-cycle CPU design?
Assume we fix the clock cycle to 200 ps for a multi-cycle CPU, what is the CPI for each instruction class and the speedup over a fixed-length clock cycle?
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