Suppose we have the following options for the ALUSel and ImmSel:

Now we are tasked to write the control signals for different instructions.

For each instruction listed below, write the corresponding control signals as a group of $13-$bit binary code

that follows the bit order below:

For control signals that are not relevant to the instruction,$\_$put $"x"$ for every bit of the control signal

As an example, the addi instruction will have the following control signals:

Here's the explanation for the addi control signals:

PCSel $=0,$ because you just execute the next instruction after addi if ever $($it$\text{'}$s not a jump or branch

instruction$),$ so you just select pc$+4$ branch. $PC+4$ branch corresponds to multiplexer input $0.$

RegWEn $=1,$ because we have to write back to the register file to save the result of the addi instruction to

rd$.$

ImmSel $=00,$ because addi is an l$-$type instruction, so you take in the l$-$type immediate. This

corresponds to $00$ according to the provided table.

BrUn$=x,$ we technically don't care about this signal because we are not executing a branch instruction,

so we put $"$X$".$

ASel $=0,$ because we have to select the output from the register file $($this is $rs1).$ Register file output $($rs$1)$

corresponds to the multiplexer input $0.$

BSel$=1,$ because we have to select the immediate for the addi instruction. Immediate generator output

corresponds to the multiplexer input $1.$

ALUSel $000,$ because we have to select the addition operation on the ALU. This corresponds to $000$

according to the provided table.

MemRW$=0,$ because we don't have to write to the memory.

WBSel $=01,$ because we have to select the output of the ALU to be written back to the register file. ALU

output corresponds to the multiplexer input $1($so binary $01).$

This $13-$bit code can then be written as $010001000001.$ Now it's your turn. For the following instructions, write the corresponding $13-$bit binary string $($without the $0$b prefix$)$ that would correspond to the control signals to properly execute the instruction. All answers should be $13$ bits long.

Q$1\mathrm{.}1$: or instruction. Q$1\mathrm{.}2$: lw instruction. Q$1\mathrm{.}3$: sw instruction $.$ Q$1\mathrm{.}4$: jal instruction. Q$1\mathrm{.}5$: bgeu instruction $($assume that the branch condition is true in this case$)$