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the ALU and the register file, then you will connect them together and run a simple machine code program on them. In order to ensure

the ALU and the register file, then you will connect them together and run a simple machine code
program on them.
In order to ensure that your design is related to yourself, various aspects of the design will be dictated by
your student ID number. These include the machine code used by your design, the contents of the register
file. This means that every student should have a unique design.
You have to work individually in this project and submit a report about your design and implementation
of this project.
Part 1
The ALU
Write a VERILOG description of an ALU with two 32-bit inputs, A and B, and a 32-bit output Result
(module alu).
The result is derived from one or both of the inputs according to the value of a 6-bit opcode. The
operations that the ALU can perform are listed below:
a + b
a - b
|a|(i.e. the absolute value of a)
-a
max (a, b)(i.e. the maximum of a and b)
min (a, b)(i.e. the minimum of a and b)
avg(a,b)(i.e. the average of a and b the integer part only and remainder is ignored)
not a
a or b
a and b
a xor b
2
The opcode that will be used to represent each of these operations is determined by the last digit of your
students ID number. The table below shows which opcode you should use in your design for each
instruction.
Digit of
ID no.
0123456789
a + b 8664634415
a b 98911215101468
|a|21018513381313
-a 101256412121187
max(a,b)12147137771073
min (a,b)1118141012146
avg(a,b)1313117996131110
not a 5151491310136152
a or b 421312814149315
a and b 113121011111554
a xor b 159453587212
So, for example if your ID is 1221438 then the last digit is 8.
Then a+b is to be represented by opcode 1, a-b is to be represented by opcode 6,|a| is to be represented
by opcode 13 and so on.(These are shown as denary (base 10) values; your design may use binary or
hexadecimal values.)
The register file
Inside a modern processor there is a very small amount of memory that is used to hold the operands that it
is presently working on. This is called the register file, and normally has the following appearance
(module reg_file).
This is a very small fast RAM, typically holding 32 x 32-bit words, and therefore requiring a 5-bit address
to select out one of the 32-bit words. It is unlike normal RAM in that it can process three addresses at the
same time, two of which are always read operations, and one of which is always written to.
Output 1 produces the item within the register file that is address by Address 1. Similarly Output 2
produces the item within the register file that is address by Address 2. Input is used to supply a value that
is written into the location addressed by Address 3.
The initial values stored in the register file are determined by the second-from-last digit of your student
ID, and are shown in the table below:
3
ID/
Location
0123456789
00000000000
17942116621264212996419811930461615034598616302
21322411562105921149055965348116408854122502994
3154621533062307070144267308112541704821658
4802695948940602676121568467867226142465474
5369214746877633226638123466784448051246784
698823288943610344100409716124328928184810836
782485932305667343930782013548730252604648
8343219784850158344150519013462892216170524
91784912340615314640614702134541044476612200
10237823801238060005400563011780670642983286
118302192654812196857223521317025861014734
12592127261305411290163241542429827354151010998
137430176280013350884026708096329497944420
14105728408129882086825841725141474074568754
157676839495667341122843003600653255803246
161238136042194743084624744108701043693009040
17160081022211914141021328412861252811900123148714
18242672621586413200467681229860146941280612008
19119301019

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