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The code segment below will be executed on a 5 - stage pipelined processor identical to the one discussed in class:AndSub OrX 5 , x

The code segment below will be executed on a 5-stage pipelined processor identical to the one discussed in class:AndSub OrX5, x2, x4Ld$14.20(x5)Add X1QxI1, x14SubSub x6, x6, x6How many cycles does this code need if executed on a pipelined RISC-V CPU that has 2 MemoriesInstruction & Data: [ You are not allowed to rearrange the code]a. Without forwarding (Ipt)

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