The following data shows two processors and their read/write operations on different cache blocks (A and B initially 0).

P1: A = 1; B = 2; A+=2; B++;

P2: C = B; D = A;

List the possible values of C and D for an implementation that ensures both of the following consistency assumptions:

1. A write does not complete (and allow the next write to occur) until all processors have seen the effect of that write.

2. The processor does not change the order of any write with respect to any other memory access.