The following machine instructions are to be executed on a computer with an instruction pipeline with four stages: I- instruction fetch, E1 register file read, E2 ALU operation and register write, and D memory access for a load (memory-to register) or store (register-to-memory) operation. A separate instruction cache and data cache is maintained by the hardware.

010 add r6,r6,r4

011 ld r1,A

012 add r1,r1,1

013 blt r1, r6, 500

014 add r3,r3,r4

015 sub r5,r5,r2

blt is a conditional branch instruction: if (r1) < (r6) then jump to instruction address 500

Draw a timing diagram for the above sequence of instructions and illustrate two types of hazards that prevent the pipeline from giving optimal performance.

Rewrite the sequence of instructions so that the pipeline can run without stopping