The following sequence of numbers represent memory addresses in a 64 word main memory: 0, 1, 2, 4, 15, 22, 12, 11, 9, 0, 38, 56, 28, 32, 40, 13, 12, 0, 18, 3

a. Assuming that a direct mapped cache is configured as a 4- line capacity 4-word blocks that has some initial data, label each reference in the list as a hit or a compulsory miss or conflict miss and show the final contents of the cache in the table .

b. Assuming that a direct mapped cache has the data capacity size of 64 bytes that is initially empty, where 1 word is 4 bytes and 1 block is 8 words. For each word memory access, indicate each reference as a hit or a miss (compulsory or conflict) and show the final contents of the cache.