The picture shows MIPS 5-stage pipeline sequence diagram with five instructions.

Assume that both IF and MEM stages are supported by a single memory.

Assume that the instruction i is a store word (sw) instruction.

Check whether any possibility of resource conflict (structure hazard) in the pipeline system or not.

If your answer is 'yes', then describe it with its possible solution(s).

1 2 7 8 9 3 EX IF ID IF ID Instruction Instruction i Instruction i + 1 Instruction i + 2 Instruction i + 3 Instruction i + 4 Clock Cycle 4 5 6 MEM WB EX MEM WB EX MEM IF ID EX ID IF ID WB MEM WB EX MEM WB IF