the processing of the ADD (with immediate operand), LD, and BR instructions.

The PC, IR, MAR, and MDR are written in various phases of the instruction cycle, depending on the opcode of the particular instruction. Irn cach location in the table below, enter the opcodes which write to the corresponding register row) during the corresponding phase (column) of the instruction cycle Fetch DecodeEvaluate Operands Execute Store result Address PC IR MAR MDR