This Assignment consists of two (2) tasks. You are required to complete both of these outside the contact hour. A detailed description of the tasks is explained below. Both of these task must be designed, simulated and implemented on Atrix A7 FPGA (Nexys) provided to you. Further, their functionalities must be verified through appropriate test strategies. Task1 Rotating and shifting Machine Introduction The aim of this task is to design a digital circuit which rotates a 4-bit input vector by a varying amount. Your design must adapt to the entity declared below. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity seven_seg_driver is port ( RotateLeft : in std_logic; en : in std_logic; N : in std_logic_vector(1 downto 0); Din : in std_logic_vector(3 downto 0); Dout : out std_logic_vector(3 downto 0) ); end seven_seg_driver; The input is applied on the port Din . The number of bits to rotate by is programmed on port N. if RotateLeft is 1, the Dout should be rotated left, otherwise right. If Enable is 0, the output on Dout should be the same as the input. Please follow the table below for further information. N Enable RotateLeft Din Dout 00 1 0 0001 0001 01 1 0 0001 1000 10 1 0 0001 0100 11 1 0 0001 0010 00 1 1 0001 0001 01 1 1 0001 0010 10 1 1 0001 0100 11 1 1 0001 1000 -- 0 - Dout=Din You are required to simulate your design using testbench. The test bench has OK signal, which should remain true. Synthesize your design to make sure the circuit does not produce any latches. The design must be critically analysed. Task 2 A 8bit Arithmetic Logic Unit (ALU) Introduction You are part of the senior design team that has been allocated a task to design a simple 8-bit ALU (Arithmetic Logic Unit). ALU is the workshop of the CPU, it carries out all the calculations, and this includes the logical operations which are applied to either the contents of the data register or the Memory Buffer Register (MBR). ALUs operations involve operations such as shift, carry, add, subtract, rotate etc. The following entity declaration is provided. Your design must adapt to the Entity below. library IEEE; use IEEE.std_logic_1164.all; entity ALU is port (A,B : in std_logic_vector(7 downto 0); Op : in std_logic_vector(3 downto 0); F : out std_logic_vector(7 downto 0); Cout : out std_logic; Equal : out std_logic); end; The Equal output is 1 if and only A = B, otherwise 0. The block diagram of an ALU is shown in figure 1.1. Note that all A and B operands are type std_logic_vector. All the arithmetic operations are evaluated using the type signed. Port Op (Op-code) is type std_logic_vector. Sixteen binary codes indicate 13 different operations and 3 unused operations. The Same binary codes are to be used for operations when the ALU is synthesized. The outputs can be any logic value for unused operations but be careful not to synthesize transparent latches. The following table shows the detailed operation of an ALU. Name Operation Op-Code Cout F (F7 to F0) A add B A+B 0000 A subtract B A-B 0001 B subtract A B-A 0010 Only A A 0100 A_7 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 Only B B 0101 B_7 B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 Negative A -A 0110 Negative B -B 0111 A shift left Shift left A 1000 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 0 A shift right Shift right A 1001 0 0A_7 A_6 A_5 A_4 A_3 A_2 A_1 A rotate left Rotate left A 1010 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 A_7 A rotate right Rotate right A 1011 0 A_0 A_7 A_6 A_5 A_4 A_3 A_2 A_1 All reset (0) F = 0 1110 0 00000000 All set (1) F= -1 1111 1 11111111 The shift operations are logical shifts, shifting one place left or right and setting the vacated bit to zero. Shift left and move bit 7 into Cout. Rotate left and move bit 7 to both bit 0 and to Cout. Rotate right move bit 0 to bit 7 (see the ALU table 1.1 above). For all the operations except shift and rotate, the inputs A and B are interpreted as signed 2s Complement 8-bit numbers, and the result is signed 9-bit numbers. The lower 8-bit of the result are to F, and the 9th bit of the result is assigned to Cout, Which is effectively the signed bit. If the result of an arithmetic operation is negative, then Cout will be set.