This has already been asked and just would like further explanations, thank you. This question is related to my previous questing. .

The processor in Q1 "bottom" is converted into a 10-stage pipeline. The slowest of these 10 stages takes 250 ps (including latch overheads).

1.What is the clock speed of this processor? (5 points)

2.What is the CPI of this processor, assuming that every load/store instruction finds its instruction/data in the instruction or data cache, and there are no stalls from data/control/structural hazards? (5 points)

3.What is the throughput of this processor (in billion instructions per second)? (10 points)

4.What is the speedup, relative to the unpipelined processor in Q1? Why is the speedup less than 10X? (10 points)

"Q1. Consider an unpipelined or single-stage processor design like the one discussed in slide 4 of lecture 16. At the start of a cycle, a new instruction enters the processor and is processed completely within a single cycle. It takes 2,000 ps to navigate all the circuits in a cycle (including latch overheads). Therefore, for this design to work, the cycle time has to be at least 2,000 pico seconds."