This is a three-part question about critical path calculation. Consider a simple single-cycle implementation of LEGv8 ISA. The operation times for the major functional components for this machine are as follows: Below is a copy of the LEGv 8 single-cycle data path design. In this implementation the clock cycle is determined by the longest possible path in the machine. The critical paths for the different instruction types that need to be considered are: R-format, Load-word, and store-word. In the table below, indicate the components that determine the critical path for the respective instruction, in the order that the critical path occurs. If a component is used, but not part of the critical path of the instruction (i.e. happens in parallel with another component), it should not be in the table. The register file is used for reading and for writing; it will appear twice for some instructions. All instructions begin by reading the PC register with a latency of 20ps. [33 points] (Question 1 Part B) Place the latencies of the components that you have decided for the critical path of each instruction in the table below. Compute the sum of each of the component latencies for each instruction. Use the total latency column to derive the following critical path information: - Given the data path latencies above, which instruction determines the overall machine critical path (latency)? - What will be the resultant clock cycle time of the machine based on the critical path instruction? - What frequency will the machine run