"timescale lns / lps module mux (input 10, 11, slct, output out); wire slot n: wire out 1; wire out 2: not (slct n, slot); and (out_1, 10, slct_n); and (out 2, 1l, slct): or (out, out_1, out_2); endmodule "timescale lns / lps module testbench(); reg 10, 11, slet; wire out; integer i; mux dt (.10 (10), Il(11), .slet (slct), .out (out)); initial begin 10=0; I1=0; slot=0; Smonitor ("eleto 200b 1.1-tub, slct, 10, 11, out): for (i=0; i