Translation of memory system with specified configuration into virtual address into physical address and access the cache.

The memory is byte addressable Memory accesses are to 1 byte words Virtual addresses are 14 bits Physical addresses are 12 bits The page size is 64 bytes TLB is 4-way set associative with total 16 total entries The L1 data cache is physically addressed and direct mapped with 4-byte line and 16 total sets. 

a) Indicate virutal address fields for virtual page offset (VPO), Virtual page number (VPN), TLB tag and TLB index.

b) Indicate physical address fields for physical page number (PPN), physical page offset (PPO), Cache tag (CT), Cache index (CI) and block offset (BO).

Please explain in detail the above address translation.