TRUE OR FALSE

1. Allowing jump and branch instructions to take fewer stages than the five required by the loading instruction increases pipeline performance.

2. In the pipelined datapath, because the control signals are generated in an earlier cycle than when used, the signals must be stored in registers.

3. In the pipelined datapath, for a math immediate instruction, the control signals ALUOp and ALUSrc are used during the instruction's 3rd stage, while RegDst and RegWrite are used in the instruction's 5th stage.

4. The MIPS pipelined control approach determines all control signal values during an instruction's 1st clock cycle, in the instruction fetch stage.