Question
Using only VERILOG coding, create a 4-bit adder/subtractor that generates CF, NF, ZF, VF condition codes. Signed 4-bit operand X3..X0 will be entered using DIP7..DIP4.
Using only VERILOG coding, create a 4-bit adder/subtractor that generates CF, NF, ZF, VF condition codes. Signed 4-bit operand X3..X0 will be entered using DIP7..DIP4. Y3..Y0 will be entered using DIP3..DIP0. The add/subtract mode will be controlled by a pushbutton switch (S2) (up for subtract, down for add). Route the 4-bit sum/difference to LED3..LED0, and route the CF, NF, ZF, and VF condition codes to LED7..LED4, respectively.
Now, change the adder/subtractor to a subtract only circuit and create a magnitude comparator that determines if X>Y, X=Y, or X
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