Using Verilog behavioral modeling, describe an n-bit circuit that has two n-bit signed inputs A and, B (represented in 2's complement), and two control inputs C1, and CO. The circuit produces an n-bit signed output Y (again represented in 2's complement), and an over flow indicator flag (1 bit that equals to 1 when there is an overflow and 0 otherwise) according to the following table: [20 marks] C1 C0 Function 00YA-B/4 01 Y ABS (A - B), i.e. Y equals the absolute difference between A & B 10 Y 1.5 B, i.e. Y equals 1 and a half of B (integer operations) 1 Y AVERAGE (A,B), i.e. Y equals the (integer) average of the 2 inputs 1 Write a test bench and simulate your circuit with the following input values (set n=5). Print the simulation results and comment on the results of each test value: [20 marks] All Values below are in decimal Set A = - 8, B = 12, Then C1,C0=(0,0), (0,1), (1,0), and (1,1) Set A = 12, B = 5, Then C1,C0=(0,0), (0,1), (1,0), and (1,1)