Vector Architecture Consider the following sequence of instructions to compute x + y + xy for two parallel vectors VO and V1. where x in VO and y in V1: addwyd V2, VO, V1 multiad V3, VO, V1 addwyd V4, V2, V3 Assume that we have a vector processor with one vector multiplication unit whose latency is 7 and one vector addition unit whose latency is 6. Let n=32 represent the length of the vector supported on our processor. The processor has fully-pipelined vector execution units. The vector processor does not supports chaining. How long would it take the original loop to execute on this processor? a.32 cycles b.120 cycles c.74 cycles d. 100 cycles e. 150 cycles f.48 cycles g.76 cycles WRONG!! h.200 cycles 1.52 cycles