VLSI

Design the layout ( you may use magic software) for a 16-bit ripple carry adder, show its logic correctness (using logic derivations) and measure its area (m2 ).

The inputs to the adder should be A15..A0, B15..B0, CIN. The outputs should be SUM15..SUM0 and COUT. The 0 bits are the least significant.

The layout area should be the bounding box of your design in other words, the smallest rectangle that can enclose your layout.

Your ADDER should instantiate full-adder (FA) cells and route them together to make a ripple carry adder.

Your FA cell may use other sub-cells if you wish, or it can be flat. You should turn in the following:

A full adder layout FA.mag (and any other cell layouts if you used more hierarchy).

Your hierarchical adder layout file ADDER.mag.

Your adder schematic files ADDER.ps (this should include all other cell schematics).

Your spice files for the adder ADDER.spc (from xcircuit), ADDER.spice (from Magic) generated from schematic/layout that pass LVS.

Your LVS setup script for the adder ADDER.tcl. (We do not require these for other subcircuits such as the FA, but you may want to make them for debugging!)

A very brief report in text format (hw3.txt) summarizing your area result in m2 and the logic explanation of your FA/ADDER. Write equations like this: !a + !(b & c)