We want to design a custom counting circuit with following properties: It has four output pattems: 0001, 001 l, 0111, 1111 There are two control signals: o go: the counter counts when it is l and the counter pauses when it is 0. o inc: the counter "increases" circulating through 0001, 001 1,0111, 1111 and wrapping around) when it is l and go is 1. The counter "decreases circulating in a reversed pattern, i.e., 1111,0111, 0011, 0001, and wrapping around) when it is 0 and go is 1. The circuit can be constructed by an FSM with four states (two D FFs). The inputs of the circuit are clk: clock signal reset: the reset signal to force the FSM to its initial state (0001) go: control signal defined above. inc: control signal defined above. The outputs of the circuit are q1, q0: outputs of D FFs, which show the current state of the FSM. m3, m2, m1, mo: outputs of the counter. 4 Procedure 4.1 Counter FSM (a) Derive the state diagram (with four states) (b) Derive the state table. (c) Perform a state assignment with a minimal number of FFs (d) Use D FFs to realize the FSM and derive the next-state truth tables and output truth table. (e) Derive next-state equations and output equation