What is the truth table for Clocked SR NOR D-Latch?

What does the circuit look like?

Need to draw a circuit for Clocked NOR D-Latched.

5. Modify the SR NOR latch to a clocked D-latch. A clocked D-latch is a data latch based on the SR NOR latch. There are two inputs: D and clock. The outputs wll still be Q and Q When the clock is zero, the D-latch remains its state. When the clock is one, the output Q will set to the input D. We will add a pre-circuit for the SR NOR latch to build a D-latch. Therefore, the outputs of the pre-circuit should drive the SR NOR latch based on the above semantics. Fill in the following characteristic table for the pre-circuit. clock