Which special purpose registers are involved in the FETCH stage of the instruction cycle? MAR, IR, MDR SRO, MAR, PC OMAR, MDR, CC OMAR, MDR, PC, IR QUESTION 4 What special purpose registers are used to interface with memory? The SR1 and SR2 The CC and ALU The IR and PC The MAR and MDR QUESTION 5 What special purpose register does the DECODE stage use to determine the instruction opcode and operands? The PC The MAR The MDR The IR Reference Figure C.3, Page 570 in your book. Which hardware element, controlled by the LC3 State Machine, selects between using an immediate value or a second source register for ADD and AND instructions? ALU O PCMUX SR2MUX REG FILE QUESTION 7 Referencing Figure C.3 again, what does the control signal ALUK that feeds the ALU decide? Which source operand to use in the calculations Whether the ALU is on or off Whether the ALU should perform an ADD, AND, or NOT If the ALU should write to memory Which special purpose registers are involved in the FETCH stage of the instruction cycle? MAR, IR, MDR SRO, MAR, PC OMAR, MDR, CC OMAR, MDR, PC, IR QUESTION 4 What special purpose registers are used to interface with memory? The SR1 and SR2 The CC and ALU The IR and PC The MAR and MDR QUESTION 5 What special purpose register does the DECODE stage use to determine the instruction opcode and operands? The PC The MAR The MDR The IR Reference Figure C.3, Page 570 in your book. Which hardware element, controlled by the LC3 State Machine, selects between using an immediate value or a second source register for ADD and AND instructions? ALU O PCMUX SR2MUX REG FILE QUESTION 7 Referencing Figure C.3 again, what does the control signal ALUK that feeds the ALU decide? Which source operand to use in the calculations Whether the ALU is on or off Whether the ALU should perform an ADD, AND, or NOT If the ALU should write to memory