With a resource allocation constrained to one multiplier and one adder (no divider is allowed), derive the Verilog program of the fully dedicated architecture (FDA) that computes the equation: a+ 2b 4 Furthermore, perform the performance analysis if the equation is to be iterated for 50 times. Instructions: Your report should contain: (1) The design of your FDA (DFG, schedule, resource allocation, RTL code, CS-Table, the functional block diagram of CU and DU), (2) Performance analysis (3) Verilog Program, the testbench program and the simulation waveform. (4) Discussion of your design and the results that you obtained. With a resource allocation constrained to one multiplier and one adder (no divider is allowed), derive the Verilog program of the fully dedicated architecture (FDA) that computes the equation: a+ 2b 4 Furthermore, perform the performance analysis if the equation is to be iterated for 50 times. Instructions: Your report should contain: (1) The design of your FDA (DFG, schedule, resource allocation, RTL code, CS-Table, the functional block diagram of CU and DU), (2) Performance analysis (3) Verilog Program, the testbench program and the simulation waveform. (4) Discussion of your design and the results that you obtained