Write a gate-level model describing the following Boolean functions: YI(A, B, C, D) = (4, 5, 6, 7, 11 ,12, 13), Y2(A, B, C. D) = (l , 2, 4. 5) And simulate it with a testbench. Same requirement for submit results. Modelsim or other Verilog simulator can be used for simulation.