write a synthesizable Verilog description of the ASM chart then write a test bench

this our code and i convert it to ASM chart

then i need to convert to Verilog code

this our information we have the code and the ASM chart

SD Input: DinL 31:0], S, reset : Output: Dout [31:0], Rdy : // inputs \& outputs declarations Integer: Count, Result, X : // some variable declarations init: X=0: Result 2=0; Count =0; Dout =0:// also reset state if (reset=1) goto init : if (S=0) goto init : if (Din 1/ if n0 ) goto loop : Dout = Result : Rdy=1: Goto init: 1) Write a synthesizable Verilog description of the circuit, a test bench, and simulate the circuit to verify its correct behavior (test it with a model size of 5 ). [ 10 points] SD Input: DinL 31:0], S, reset : Output: Dout [31:0], Rdy : // inputs \& outputs declarations Integer: Count, Result, X : // some variable declarations init: X=0: Result 2=0; Count =0; Dout =0:// also reset state if (reset=1) goto init : if (S=0) goto init : if (Din 1/ if n0 ) goto loop : Dout = Result : Rdy=1: Goto init: 1) Write a synthesizable Verilog description of the circuit, a test bench, and simulate the circuit to verify its correct behavior (test it with a model size of 5 ). [ 10 points]