Write a VHDL architecture for the entity below:

entity r3by1 is

port(a,b,c,d: in bit;

x,y,z: out bit);

end r3by1;

The architecture must implement the following logic functions:

x(a,b,c,d)=(3,4,6,7,11,12,14,15)x(a,b,c,d)=(3,4,6,7,11,12,14,15)

y(a,b,c,d)=(2,6,9,10,11,13,14,15)y(a,b,c,d)=(2,6,9,10,11,13,14,15)

z(a,b,c,d)=(5,7,8,10,12,13,14,15)z(a,b,c,d)=(5,7,8,10,12,13,14,15)

Directions:

• A testbench and other resources are posted below this assignment. Use the testbench provided to test your code.
• You're not required to simplify the functions. However, doing so may make it easier to implement.
• Credit will be awarded based on how many of the test cases in the testbench pass.

Use the circuit in the last problem to answer the following question.

Treat the input bits abc as a 3-bit value that is transformed into a 3-bit output value xyz. The 1-bit input signal d determines exactly how abc is transformed into xyz.

What operation is the circuit performing?

Test Bench:

library IEEE; use IEEE.numeric_bit.all;

entity testbench is end testbench;

architecture tb of testbench is

component r3by1 is port(a,b,c,d: in bit; x,y,z: out bit); end component r3by1;

-- input stimulus vector for inputs: a, b, c, d signal abcd_in: bit_vector(3 downto 0);

-- output response vector for ouputs: x, y, z signal xyz_out: bit_vector(2 downto 0);

-- expected output vector signal xyz: bit_vector(2 downto 0);

begin

-- instantiate Device Under Test (DUT) DUT: r3by1 port map(abcd_in(3), abcd_in(2), abcd_in(1), abcd_in(0), xyz_out(2), xyz_out(1), xyz_out(0)); process begin -- loop through each row of the truth table l_test : for k in 0 to 15 loop

-- generate input vector abcd_in <= bit_vector(to_unsigned(k, abcd_in'length)); -- generate expected output vector wait for 5 ns; if abcd_in(0)='1' then xyz <= abcd_in(1) & abcd_in(3 downto 2); else xyz <= abcd_in(2 downto 1) & abcd_in(3); end if; -- verify output matches expected value wait for 5 ns; assert(xyz_out=xyz) report "input of abcd=" & integer'image(k) & " results in xyz=" & integer'image(to_integer(unsigned(xyz_out))) & " (EXPECTED " & integer'image(to_integer(unsigned(xyz))) & ")" severity error; end loop l_test; assert false report "Testing complete." severity note; wait; end process; end tb;