• •  
  • 
    

Write VHDL code for an N-but add/sub-component which adds when the select input is 0 and subtracts when it is 1. Please do this using dataflow modeling. Please provide two ways to solve it. The first way should be using logical gates, and the second way should be using '' and '-' operators. There should be 3 inputs (A, B, Sel) and 2 outputs (Sum, Carry). Both methods should use dataflow modeling.