You are investigating the possible benefits of a way-predicting L1 cache. Assume that a 64 KB four-way set associative single banked L1 data cache is the cycle time limiter in a system. As an alternative cache organization you are considering a way-predicted cache modeled as a 64KB direct-mapped cache with 80% prediction accuracy. The cycle time of the 64KB 4-way cache is 0.83ns. Assume that a mispredicted way access that hits in the cache takes one more cycle. Assume the miss rate for a 4-way 64 KB cache is 0.33%, and that the miss penalty for the direct mapped cache is 20 cycles. The 64KB direct mapped cache can be accessed in 0.5ns.

a. What is the average memory access time of the current cache (in cycles) versun the way-predicted cache?

Note that the way-predicted cache has cycle time and access time similar to direct mapped cache, and miss rate similar to 4-way cache.

b. If all other components could operate with the faster way-predicted cache cycle time (including the main memory), what would be the impact on performance from using the way-predicted cache?

c. Way-predicted caches have usually been used only for instruction caches that feed an instruction queue or buffer. Imagine that you want to try out way prediction on a data cache. Assume that you have 80% prediction accuracy and that subsequent operations (e.g., data cache access of other instructions, dependent operations) are issued assuming a correct way prediction. Thus, a way mis-prediction necessitates a pipe flush and replay trap, which requires 15 cycles. Is the change in average memory access time per load instruction with data cache way prediction positive or negative, and how much is it?