You have been assigned to design a 8M x 32 bit memory board. You may use only 256K x 8 bit RAM chips with full parallel addressing. a. How many bits are required in the Address Bus (i.e. MAR) of the whole board? b. How many address pins are required per chip? c. How many data pins are required per chip? d. How many of the system address lines must be split-off and decoded for input into Chip-Enable pins. e. Consider the physical memory address X = 724288. In the memory matrix design, which row would contain this address? (Note that you need to provide the row number and the rows start from 0. As an example, if an address is on the fifth row, the row number is 4).

2. (40 points) Consider a 2-way set associative cache organization with the capacity of 8 blocks. Assume Write-Allocate and Write-back are used. Further, assume that the replacement algorithm is LRU. Show the content of the cache and the content of the memory locations for each block after each access. If an entry is left blank in the memory portion, it is assumed that the value of the entry will be the block that occupied the entry most recently. For the cache portion, show both entries for any access to a set (read or write) - if no access is made to a set, the most recent values are assumed (so no need to repeat the entry) As a notation, for each access, the word Read/Write followed by a number indicates the type of access for that block number. For example, Read 5 indicates that the cache needs to read a word within block 5. As a further notation, a modification (write) to a block is indicated by superscripting it with the prime character. For example, the first modification to block 5 is indicated as 5, the second as 5, etc.

Block Access CO C1 C2 C3 MO M1 M3 M4 M5 M6 M7 M8 M9 M11 write 5 Write 9 Write 7 Read 5 write 5 Write 1 Read 3 Write 8 Read Write 9 Write 4 Write 11