You have been assigned to design a 8M x 32 bit memory board. You may use only 256K x 8 bit RAM chips with full parallel addressing.

a. How many bits are required in the Address Bus (i.e. MAR) of the whole board?

b. How many address pins are required per chip?

c. How many data pins are required per chip?

d. How many of the system address lines must be split-off and decoded for input into Chip-Enable pins.

e. Consider the physical memory address X = 724288. In the memory matrix design, which row would contain this address? (Note that you need to provide the row number and the rows start from 0. As an example, if an address is on the fifth row, the row number is 4).