You have been designated to design a

$3$

$2$

$$KB

$4$

$-$

$$way set associative cache. Each block in the memory is

$1$

$6$

$$Bytes$.$ The cache should be Virtually Indexed Physically Tagged type to avoid aliasing. The virtual address is

$3$

$6$

$$bits long. The physical address is

$3$

$2$

$$bits long. Page offset has the same length

$($

number of bits

$)$

$$in both the virtual and physical address. We know that the physical page offset is the total number of bits of the byte offset and set index.

a

$)$

$$What is the page size?