You need to fill in the guts of the individual building blocks and a few high-level connections. The rest is done for you

// N-bit Adder/Subtractor (active low subtract)

module addsub #(parameter dw=8) ( input [dw-1:0] dataa, // incoming operand input [dw-1:0] datab, input add_sub, // 1: add; 0: subtrac input clk, output logic [dw-1:0] result // sum or difference ); // fill in guts //add_sub result //1 dataa + datab; //0 dataa - datab; endmodule

Turn in:

1. Full working set of Verilog code, either the full set of individual files or a .zip thereof.

2a. Screenshot of your ModelSim transcript, showing the expected results vs. yours.

2b. Screenshot of any remaining unresolved warning messages from ModelSim.

3. Screenshot of a portion of your ModelSim waveform viewer, showing a done flag / reset cycle, the incoming operand values, and the product value.

4a-c. Screenshot of your Quartus RTL VIewer schematics; top level (control block and data path block), then the top level of each of these two blocks (3 diagrams in all).

5. A brief discussion of:

5.1. Annotated list of errors, if any, in your product results reported on your ModelSim transcript (or "everything worked");

5.2. Annotated list of unresolved warning messages from ModelSim transcript (e.g. mismatched port sizes);

5.3 Repeat 5.3 for warning or error messages from Quartus;

5.4 This design has a bug that gives the wrong product for large-magnitude negative operands. Modify the test bench with a nested for loop to identify the threshold at which this occurs.

5.5 Anything that might help TAs or me navigate through what your turned in (very brief for most of you)