4. Explore different synthesis options for the ALU from problem 3. Change the area and speed synthesis settings in the compiler under Assignments DSettings DAnalysis and Synthesis Settings, rerun the timing analyzer to determine speed, and examine the report file for hardware size estimates. Include data points for the default, optimized for speed, balanced, and optimized for area settings. Build a plot showing the speed versus area trade-offs possible in the synthesis tool. Use the logic element (LE) device utilization percentage found in the compilation report to compare the size of the designs.