Questions and Answers of Rapid Prototyping Of Digital Systems

9. For a more challenging problem, port the eCos operating system to a DE Board. It is available free at www.niosforum.com. First, run a simple hello world application using the UART. For the second
7. Obtain the licenses needed for the MicroC/OS-II Nios II OS port. The license for the Nios II MicroC/OS-II port is available from Micrium (www.micrium.com) and a full commercial license for the
6. Create a new HTML page on your PC and save it to a USB flash drive. Insert the drive into the USB slot on the DE2 board. Mount the drive as discussed in the chapter. Delete the
5. Using the ps, kill, and free commands, try stopping and starting the dhcdcd, inetd, telnetd, ftpd, and boa programs one at a time. Record the approximate memory required for each program to run.
4. Using the ps, kill, and free commands, try stopping and starting the nano-X, nanowm, and other graphical programs one at a time. Record the approximate memory required for each program to run.
3. Follow the instructions in the chapter for establishing a network connection on the DE2 board and starting the boa web server. To demonstrate the working system, open a web browser on your PC and
2. Load a small (~20KB) JPEG image onto a USB flash drive. Insert the drive into the USB slot on the DE2 board. Mount the drive as discussed in the chapter and use the nxview program to display the
1. In Figure 18.4, notice that the clock frequency is set to 100 MHz. To handle the computational needs of an operating systems, the clock rate was increased from the 50 MHz clock used in Chapter 17.
13. Program a complete Nios II design into both Flash memories so that the FPGA board loads both the FPGA hardware configuration data and the software from the two Flash memories automatically at
12. Program the FPGA’s serial flash device so that your Nios II hardware design loads automatically at power up. See Appendix E for instructions on programming the FPGA’s serial flash
11. Interface the dual port video display memory used in one of the earlier problems directly to the Avalon system bus instead of using PIO ports. See the Avalon Interface Specification Manual.
10. Add a custom instruction to the Nios II processor designed to speed up a particular application area. See the Nios II Custom Instruction User Guide. Demostrate the speedup obtained with the new
9. After solving the previous two problems, develop software for a video game that uses the mouse or keyboard for input and displays output on the monitor. If you need graphics for your game,
8. Use the video sync core and character generation ROM from Chapter 10 to add a video text display to the Nios processor. Add a dual port memory to store a screen full of characters. Write charcters
7. Interface a PS/2 keyboard or mouse to the Nios II processor using PIO ports. Write software to demonstrate the new keyboard or mouse interface. Display the output on the LCD or the UART. There are
6. Design an automatic setback HVAC thermostat using the FPGA. Interface a temperature sensor to the FPGA. Some temperature sensors are available with digital outputs that would not require a
5. Implement one of the FPGA robotics projects from Chapter 13 using a Nios II processor running C code. See problem 1 for robot interface suggestions.
4. Add an SPI interface to the Nios II hardware design and use it to interface to an external SPI device connected to one of the FPGA board’s expansion connectors.
3. Add a parallel port to the Nios II hardware design. Use two 8-bit ports, one for data and one for status and control bits. Connect the PIO port’s I/O bits to the parallel port connector on the
2. Add a PIO port to the Nios II hardware design and use the PIO port’s I/O bits to design an I2 C hardware interface to the FPGA board’s real-time clock chip. Software will be needed to send I2
1. Add two 8-bit PIOs to the Nios II hardware design that connect to the 5 volt I/O pins on the board’s header connector. Setup one port for input and one port for output. Connect the PIO port’s
Specify the top-level pin assignments and project settings necessary for implementing the Nios processor on the DE boards.
Create a PLL that supplies a clock signal for the on-board SDRAM, and
Generate a custom Nios II processor core,
Navigate Altera’s SOPC Builder (Nios II processor design wizard),
6. Port an interesting C application program to the Nios II processor. Execute the application from SDRAM.
5. Write a retro version of the 1970’s classic kill the bit computer game for the DE board.The goal in the kill the bit game is to turn off all of the four LEDs using the four pushbuttons. The game
4. Memory test programs cannot test all possible patterns. Research the various algorithms widely used in more thorough memory test programs and write your own more advanced memory test program for
3. Expand the C program in the previous problem to display the elapsed time in hours, minutes, and seconds on the LCD (or seven-segment displays). Have one pushbutton reset the time to zero and
2. Write a C program that displays a count of the seconds that the program has been running in the LCD display on the DE2 board or on the seven-segment displays on the DE1 board. Demonstrate the
1. Write a C program to blink the eight green LEDs in a reversing shift pattern on the DE board. After the last LED in each direction turns on, reverse the direction of the shift.Run and demonstrate
19. Develop a VHDL synthesis model for another RISC processor’s instruction set. Possible choices include the Nios, Microblaze, Picoblaze, PowerPC, ARM, SUN SPARC, the DEC ALPHA, and the HP PARISC.
18. The MIPS VHDL model was designed to be easy to understand. Investigate various techniques to increase the clock rate such as using two dual-port memory blocks for the register file, moving
17. Add programmed keyboard input and video output to the sort program from the previous problem using the keyboard, vga_sync, and char_rom FPGAcores. Use a dedicated memory location to interface to
16. Add the required instructions to the model to run the MIPS bubble sort program from Chapter 3 of Computer Organization and Design The Hardware/Software Interface
15. Investigate using two Altsyncram memory blocks to implement the register file in IDECODE. A single Altsyncram block can be configured to do a read and write in one clock cycle (dual port). To
14. Add the overflow exception hardware suggested at the end of Chapter 6 in Figure 6.42 of Computer Organization and Design The Hardware/Software Interface by Patterson and Hennessy. Add an overflow
13. Redesign the pipelined MIPS VHDL model so that branch instructions have 1 delay slot as seen in Figure 6.40 (i.e. one instruction after the branch is executed even when the branch is taken).
12. Use the timing analyzer to determine the maximum clock rate for the pipelined MIPS implementation, verify correct operation at this clock rate in a simulation, and compare the clock rate to the
11. When a branch is taken, several of the instructions that follow a branch have already been loaded into the pipeline. A process called flushing is used to prevent the execution of these
10. Add LW/SW forwarding to the pipelined model. This will allow an LW to be followed by an SW that uses the same register. It is possible since the MEM/WB register contains the load instruction
9. Once the MIPS is pipelined as in problem 8, data hazards can occur between the five instructions present in the pipeline. As an example consider the following program:
8. Pipeline the MIPS VHDL simulation. Test your VHDL model by running a simulation of the example program shown in Figure 6.21 using the pipeline hardware shown in Figure 6.27 in Computer
7. Add and test the R-format SLT, set if less than, instruction. As an example SLT $1, $2,$3 performs the operation, If $2
6. Add and test the I-format ADDIU, add immediate unsigned, instruction. Modifications to the existing VHDL MIPS model will be required.
5. Add and test the BNE, branch if not equal, instruction. Modifications to the existing VHDL MIPS model will be required. Hint: Follow the implementation details of the existing BEQ, branch if
4. Add and test the JMP instruction. The JMP or jump instruction is not PC-relative like the branch instructions. The J-format JMP instruction loads the PC with the low 26 bits of the instruction.
3. Write a MIPS test program for the AND, OR, and SUB instructions and run it on the VHDL MIPS simulation. These are all R-format instructions just like the ADD instruction. Modifications to the
2. Recompile the MIPS model using the VIDEO_MIPS.VHD file, which generates video output. Download the design to the FPGA board. Attach a VGA monitor to the FPGA board. Single step through the program
1. Use VHDL to synthesize the MIPS single clock cycle design in the file TOP_SPIM.VHD. After synthesis and simulation perform the following steps:Display and print the timing diagram from the
Robots that detect mines
Robots that collect objects
Fire Fighting Robots
Robot Laser Tag
Robot Soccer Teams
Sumo Wrestling
Robot Dance Contest
Robot Maze Solving
22. Develop and hold a FPGA-bot design contest. Information on previous and current robotics contests can be found online at various web sites. Here are some ideas that have been used for other robot
21. Use a Nios processor to control the robot with C code using the UP3 Nios II reference design in Chapters 16 & 17.
20. Use the μP 3 computer from Chapter 8 to implement a microcontroller to control the robot instead of a custom state machine. Write a μP 3 assembly language program to solve one of the previous
19. Interface additional sensors, switches, etc., to the FPGA-bot so that it can navigate a maze. If several robots are being developed, consider a contest such as best time through the maze or best
18. Attach several IR ranging sensors to the FPGA-bot and use the sensor data to develop a wall following robot.
17. Attach the Sonar transducer to an unmodified servo’s output shaft. Use the new servo to scan the area and locate the closest object. To sweep the unmodified servo back and forth, a timing pulse
Move close to the object and stop.
Locate the nearest object.
Scan the immediate area 360 degrees by rotating the robot
16. Interface a Sonar-ranging module to the FPGA-bot and perform the following operation:
Move forward 4 seconds.
Turn North.
15. Interface the a magnetic or electronic compass module to the FPGA-bot, and design a state machine that performs the following operation:
14. Using a standard IR remote control unit from a television or VCR and an IR sensor interfaced to the FPGA-bot, implement a remote control for the FPGA-bot. Different buttons on the remote control
13. Interface the line-following module to the FPGA-bot, and design a state machine that follows a line. The line-following module has three sensor signals, left, center, and right. If the line
12. With two FPGA-bots facing each other, develop a serial communications protocol using the IR LEDs and sensors. Assume the serial data is fixed in length and always starts with a known pattern at a
11. Once the IR proximity sensor module from problem 8 is interfaced, design a state machine for the robot that moves forward and avoids obstacles. If it sees an obstacle to the left, turn right, and
10. Use motor speed control and a state machine with a timer to perform a small figure eight with the FPGA-bot.
9. Using IR sensor input, develop a design for the FPGA-bot that follows a person. The person must be within a foot or so of the FPGA-bot. When a left signal is present turn left, when a right signal
8. Interface an IR proximity sensor module to the FPGA-bot using jumpers connected to the Cyclone male header socket. Attach the module in front of the header socket using foam tape. Alternate
7. Using the keyboard FPGAcore, design an interface to the keyboard that allows the keyboard to be used as a remote control device to move the robot. Pick at least five different keys to command to
6. Using a ROM, develop a ROM-based state machine that reads a motor direction and time from the ROM. Put a complex pattern such as a dance step in the ROM using a MIF file. For looping, another
Stop, pause for 2 seconds, turn 180 degrees, and start over.Determine the amount of time required for 90- and 180-degree turns by trial and error. A 10Hz or 100Hz clock should be used for the timer.
Turn left and go forward for 2 seconds.
Turn right and go forward for 4 seconds (do not count the time it takes to turn).
Move forward for 6 seconds.
5. Design a state machine using a counter/timer that will move the robot in the following fixed pattern:
4. Use an IR LED and IR sensor to add position feedback to the motors. You can build it yourself or a similar servo wheel encoder kit built by Nubotics is available from Acroname. Some sensor modules
3. Develop a speed controller for the robot drive motors by pulsing the drive motors on and off. The motors are sent a pulse of 1ms for reverse and 2ms for forward at full speed. If no pulse is sent
2. Using the dead zone settings from problem 1, design a motor speed controller. Settings within around .2ms of the dead zone will make the motor run slower. The closer to the dead zone the slower
1. Develop a counter design to find the dead zone of a converted R/C servo motor. The dead or null zone is the time near 1.5ms that actually makes the servo motor stop moving. As in the example motor
21. Blue Loctite, Cyanoacrylate (CA) Glue, and Clear Silicone RTV. These adhesives and glues are useful to secure screws, servos, and wheels. The mechanical vibration on moving robots tends to shake
20. Four 4-40 Screws 5/16-inch or slightly longer. The screws are used to attach the UP3 board to Plexiglas. The screws thread into the hex spacers attached to the UP3 board.
19. Approximately 8 inches of 1-inch wide double-sided 3M foam tape. This is used to attach servos, skids, and optional sensor boards to the base. Be sure to clean surfaces to remove any grease or
18. One 8-inch long strip of 2-inch wide sticky-back Velcro. Two 8-inch long strips, 1 inch wide can also be used. The Velcro is used to attach the battery to the bottom of the Plexiglas base. Since
17. 3/16-inch thick Plexiglas cut into a 10.5-inch diameter circle. This part is the base of the robot. Colored Plexiglas such as opaque white, will not show scratches as easy as clear. Holes to
16. Four, 1-inch hex spacers with 4-40 threads or use the shorter spacers that come with the board. These are used to mount the UP3 board to the Plexiglas base using the holes in the UP3 board.
15. An assortment of small wire jumpers and connectors to attach wires to the male headers on the UP3. These are the jumper wires commonly used for protoboards. Two short jumpers are used to connect
14. A Coaxial DC Power Plug with 5mm O.D. and 2.1mm I.D., Radio Shack Number 274-1567 or equivalent. This power plug fits the power socket on the UP3 board. A different size plug is needed for the
13. A 1-inch piece of small heat shrink tubing or electrical tape. This part is used to insulate a splice in the twin-lead power wire.
12. Approximately 9 inches of small-gauge twin-lead speaker wire. This part is used to connect power to the UP3 board. The wire must fit into the DC power plug (part# 11).Typically, 20-22 gauge wire
11. A miniature toggle switch with solder lug connections. The switch should have a contact rating of more than two amps (Radio Shack #275-635B or equivalent). Only two contacts or single pole single

Showing 1 - 100 of 385