Rapid Prototyping Of Digital Systems 2nd Edition James O Hamblen, Tyson S Hall, Michael D Furman - Solutions

Unlock the full potential of "Rapid Prototyping of Digital Systems 2nd Edition" by accessing a comprehensive collection of resources tailored for your learning needs. Explore our online platform, offering a complete answers key and detailed solutions manual, including solutions in PDF format. Dive into solved problems with step-by-step answers that illuminate the textbook's concepts. Whether you're seeking chapter solutions or a complete test bank, our resources serve as an invaluable instructor manual. Enhance your understanding with these questions and answers, all available for free download. Elevate your learning journey with these indispensable tools.

5. Create and defend a property level organizational structure for an integrated revenue function as discussed in the chapter and described in the case study in the revenue management perspectives section.
4. Of the skills mentioned in this chapter, which two do you think are the most critical for the revenue manager of the future?How would you evaluate a candidate to determine whether they possessed this skill set?
3. Recommend a revenue management organizational structure for a 300-property, highly franchised, economy scale chain.What kind of technology solutions would you recommend to support that function?
2. If you had to find revenue management talent outside of the hospitality and travel industry, what type of industries would you target, and what roles within those industries? Why?
1. Describe how the evolution of the revenue management discipline has impacted the skill set required for a revenue manager.
4. What data and technology challenges will hotels encounter as they start to work toward personalization?
3. How does personalization relate to customer‐centric revenue management? What are some of the dangers associated with personalized pricing?
2. Where and how should revenue management be involved in a personalization initiative? (i.e., what parts of the guest journey does revenue management provide information for, and how is that information consumed by the guest and the operation)?
1. In this chapter, I gave the example of Ann Roberts, a business traveler, looking for a weekend getaway. Provide several examples of the importance of understanding the context of an interaction as opposed to just matching the web visitor or guest to their profile.
5. Explain how you might set up the “red, yellow, green” recommendation system I describe earlier if you were the revenue manager of a chain of 200 small, roadside economy hotels, including the actions you’d expect the hotel managers to take under each condition.
4. Describe a scenario when you might make a strategic decision to override the revenue management system’s price recommendations to offer a lower market price.
3. Explain how familiarity and framing impact consumers’ perceptions of price fairness.
2. Why is the concept of a customer reference price so important for revenue managers to understand?
1. Give an example of a situation where a hotel might be in danger of violating the Principle of Dual Entitlement.
6. What are some challenges associated with guest‐centric revenue management programs? How would you overcome these challenges?
5. If you were going to kick off a spa revenue management program, who would you invite to the first meeting? What data would you ask the team to collect to establish the baseline?
4. What is the right RevPATI for spa? Which of the three levers(price, time, space) can spa utilize?
3. Why is it important to use the metric Revenue per Available Time Based Inventory Unit as a baseline and tracking mechanism?
2. Describe why spas meet all the necessary conditions to apply revenue management.
1. What are the necessary conditions for revenue management?List an example of why that condition is important for the application of revenue management.
6. Describe how hotels should think about incorporating customer value into the revenue management decision.
5. Design a promotion and describe which elements were produced by each of the functional areas: customer analytics, revenue management, campaign management, marketing optimization.
4. How would you change the revenue manager’s incentive structure to incorporate the vision of intelligent demand management? What about the marketer’s incentive structure?
3. If you were a revenue manager evaluating demand for the spring, what information would you need from marketing to ensure accurate demand forecasts and how would you incorporate that information?
2. If you were a marketer designing a promotion for the spring, what information would you want from revenue management, and how would you incorporate that into the promotion plan?
1. What functions would a cross‐functional team with the goal of intelligent demand management be comprised of at the property level? How about at corporate?
4. If a hotelier told you they were working on a campaign to improve their TripAdvisor rank, what advice would you give them?
3. Provide one example for each of the four quadrants from Figure A.10 in the Appendix of how you would use inbound and outbound social media communication for a tactical or strategic business problem.
2. If you were primarily a business hotel, how might you think about reputation management, versus if you were a resort property with primarily a leisure market?
1. What are three issues that make reputation data challenging for revenue managers to work with?
5. What are two issues that could arise when you add more variety of data into an analytical model?
4. What value would airline lift into a market provide for a revenue manager? What might some of the dependencies be?
3. Why is weather data problematic in a forecast? How would it benefit a forecast?
2. For each of the data sources below, apply the list of questions from this chapter, come up with a list of information you would need from the data provider to be certain of the value of that data, and determine how it might be useful in revenue management decision making:a. Forward‐looking
1. How could review and rating data be used in revenue management decision making?
6. How is this different from a traditional revenue management methodology?
5. How would the revenue manager interpret a demand forecast if they were using a price optimization methodology?
4. What type of pricing methodology—price optimization, or revenue management—would be best for an economy hotel, a limited service, and a full‐service? What characteristics of their demand would you use to make this determination?
3. What is the difference between yielding and price optimization?
2. What is price endogeneity and how and why does it impact hotels?
1. Define the traditional revenue management optimization problem in terms of objective, decision variables, and constraints.
9. For a more challenging problem, port the eCos operating system to a DE Board. It is available free at www.niosforum.com. First, run a simple hello world application using the UART. For the second test, write a multithreaded application with one thread talking to the UART and a second thread
7. Obtain the licenses needed for the MicroC/OS-II Nios II OS port. The license for the Nios II MicroC/OS-II port is available from Micrium (www.micrium.com) and a full commercial license for the Altera tools for schools is available from Altera’s University Program (www.altera.com). Micrium also
6. Create a new HTML page on your PC and save it to a USB flash drive. Insert the drive into the USB slot on the DE2 board. Mount the drive as discussed in the chapter. Delete the /home/httpd/index.html file using the rm command. Then replace the index.html file with a symbolic link to the HTML
5. Using the ps, kill, and free commands, try stopping and starting the dhcdcd, inetd, telnetd, ftpd, and boa programs one at a time. Record the approximate memory required for each program to run. Create a table that lists the processes and memory requirements for these five µClinux programs.
4. Using the ps, kill, and free commands, try stopping and starting the nano-X, nanowm, and other graphical programs one at a time. Record the approximate memory required for each program to run. Create a table that lists the processes and memory requirements for at least five µClinux programs.
3. Follow the instructions in the chapter for establishing a network connection on the DE2 board and starting the boa web server. To demonstrate the working system, open a web browser on your PC and view the web page being served by the web server by entering the DE2 board’s IP address as the URL
2. Load a small (~20KB) JPEG image onto a USB flash drive. Insert the drive into the USB slot on the DE2 board. Mount the drive as discussed in the chapter and use the nxview program to display the image. Make sure that there is sufficient memory available before you run the nxview program.
1. In Figure 18.4, notice that the clock frequency is set to 100 MHz. To handle the computational needs of an operating systems, the clock rate was increased from the 50 MHz clock used in Chapter 17. Changing the clock frequency required several changes in the PLL settings that generate the
13. Program a complete Nios II design into both Flash memories so that the FPGA board loads both the FPGA hardware configuration data and the software from the two Flash memories automatically at power up. See the Nios II Flash Programmer User Guide and study the section on how to port the Flash
12. Program the FPGA’s serial flash device so that your Nios II hardware design loads automatically at power up. See Appendix E for instructions on programming the FPGA’s serial flash configuration chip.
11. Interface the dual port video display memory used in one of the earlier problems directly to the Avalon system bus instead of using PIO ports. See the Avalon Interface Specification Manual.
10. Add a custom instruction to the Nios II processor designed to speed up a particular application area. See the Nios II Custom Instruction User Guide. Demostrate the speedup obtained with the new instruction by running the application with and without the new instruction.
9. After solving the previous two problems, develop software for a video game that uses the mouse or keyboard for input and displays output on the monitor. If you need graphics for your game, consider replacing the character memory and text display with a larger memory containing only pixels used
8. Use the video sync core and character generation ROM from Chapter 10 to add a video text display to the Nios processor. Add a dual port memory to store a screen full of characters. Write charcters to the dual port memory from the Nios II processor using PIO ports added to the Nios II design. The
7. Interface a PS/2 keyboard or mouse to the Nios II processor using PIO ports. Write software to demonstrate the new keyboard or mouse interface. Display the output on the LCD or the UART. There are two major options to consider, use the keyboard and mouse cores from Chapter 11 or do everything in
6. Design an automatic setback HVAC thermostat using the FPGA. Interface a temperature sensor to the FPGA. Some temperature sensors are available with digital outputs that would not require a separate analog-to-digital IC. Display the current time, temperature, heat, fan, and A/C status, and the
5. Implement one of the FPGA robotics projects from Chapter 13 using a Nios II processor running C code. See problem 1 for robot interface suggestions.
4. Add an SPI interface to the Nios II hardware design and use it to interface to an external SPI device connected to one of the FPGA board’s expansion connectors.
3. Add a parallel port to the Nios II hardware design. Use two 8-bit ports, one for data and one for status and control bits. Connect the PIO port’s I/O bits to the parallel port connector on the FPGA board. Software will be needed to monitor and control the handshake lines (see Section 12.1)
2. Add a PIO port to the Nios II hardware design and use the PIO port’s I/O bits to design an I2 C hardware interface to the FPGA board’s real-time clock chip. Software will be needed to send I2 C commands, the PIO port just provides a hardware interface to the I2 CSDA and SLC bits (see Section
1. Add two 8-bit PIOs to the Nios II hardware design that connect to the 5 volt I/O pins on the board’s header connector. Setup one port for input and one port for output. Connect the PIO port’s I/O pins to eight input pins and eight output pins on the header. This is a handy way to interface
Specify the top-level pin assignments and project settings necessary for implementing the Nios processor on the DE boards.
Create a PLL that supplies a clock signal for the on-board SDRAM, and
Generate a custom Nios II processor core,
Navigate Altera’s SOPC Builder (Nios II processor design wizard),
6. Port an interesting C application program to the Nios II processor. Execute the application from SDRAM.
5. Write a retro version of the 1970’s classic kill the bit computer game for the DE board.The goal in the kill the bit game is to turn off all of the four LEDs using the four pushbuttons. The game starts with an initial non-zero pattern displayed in the LEDs. The pattern constantly does a
4. Memory test programs cannot test all possible patterns. Research the various algorithms widely used in more thorough memory test programs and write your own more advanced memory test program for SRAM. Most memory test programs use several algorithms to check for different types of faults.
3. Expand the C program in the previous problem to display the elapsed time in hours, minutes, and seconds on the LCD (or seven-segment displays). Have one pushbutton reset the time to zero and another pushbutton start and stop the timer just like a stopwatch.
2. Write a C program that displays a count of the seconds that the program has been running in the LCD display on the DE2 board or on the seven-segment displays on the DE1 board. Demonstrate the program on the DE board.
1. Write a C program to blink the eight green LEDs in a reversing shift pattern on the DE board. After the last LED in each direction turns on, reverse the direction of the shift.Run and demonstrate the program on the DE board. Recall that C supports shift operations (“”) and you will need a
19. Develop a VHDL synthesis model for another RISC processor’s instruction set. Possible choices include the Nios, Microblaze, Picoblaze, PowerPC, ARM, SUN SPARC, the DEC ALPHA, and the HP PARISC. DVD Appendix D of Computer Organization and Design The Hardware/Software Interface contains
18. The MIPS VHDL model was designed to be easy to understand. Investigate various techniques to increase the clock rate such as using two dual-port memory blocks for the register file, moving hardware to different pipeline stages to even out delays, or changing the way memory is clocked.
17. Add programmed keyboard input and video output to the sort program from the previous problem using the keyboard, vga_sync, and char_rom FPGAcores. Use a dedicated memory location to interface to I/O devices. Appendix A.36-38 of Computer Organization and Design The Hardware/Software Interface
16. Add the required instructions to the model to run the MIPS bubble sort program from Chapter 3 of Computer Organization and Design The Hardware/Software Interface
15. Investigate using two Altsyncram memory blocks to implement the register file in IDECODE. A single Altsyncram block can be configured to do a read and write in one clock cycle (dual port). To perform two reads, use two Altsyncrams that contain the same data (i.e. always write to both blocks).
14. Add the overflow exception hardware suggested at the end of Chapter 6 in Figure 6.42 of Computer Organization and Design The Hardware/Software Interface by Patterson and Hennessy. Add an overflow circuit that produces the exception with a test program containing an ADD instruction that
13. Redesign the pipelined MIPS VHDL model so that branch instructions have 1 delay slot as seen in Figure 6.40 (i.e. one instruction after the branch is executed even when the branch is taken). Rewrite the VHDL model of the MIPS and test the program from the problem 10 assuming 1 delay slot. Move
12. Use the timing analyzer to determine the maximum clock rate for the pipelined MIPS implementation, verify correct operation at this clock rate in a simulation, and compare the clock rate to the original non-pipelined MIPS implementation.
11. When a branch is taken, several of the instructions that follow a branch have already been loaded into the pipeline. A process called flushing is used to prevent the execution of these instructions. Several of the pipeline registers are cleared so that these instructions do not store any values
10. Add LW/SW forwarding to the pipelined model. This will allow an LW to be followed by an SW that uses the same register. It is possible since the MEM/WB register contains the load instruction register write data in time for use in the MEM stage of the store.Write a test program and verify
9. Once the MIPS is pipelined as in problem 8, data hazards can occur between the five instructions present in the pipeline. As an example consider the following program:
8. Pipeline the MIPS VHDL simulation. Test your VHDL model by running a simulation of the example program shown in Figure 6.21 using the pipeline hardware shown in Figure 6.27 in Computer Organization and Design The Hardware/Software Interface. To minimize changes, pipeline registers must be placed
7. Add and test the R-format SLT, set if less than, instruction. As an example SLT $1, $2,$3 performs the operation, If $2
6. Add and test the I-format ADDIU, add immediate unsigned, instruction. Modifications to the existing VHDL MIPS model will be required.
5. Add and test the BNE, branch if not equal, instruction. Modifications to the existing VHDL MIPS model will be required. Hint: Follow the implementation details of the existing BEQ, branch if equal, instruction and a change to add BNE should be obvious.Both BEQ and BNE must function correctly in
4. Add and test the JMP instruction. The JMP or jump instruction is not PC-relative like the branch instructions. The J-format JMP instruction loads the PC with the low 26 bits of the instruction. Modifications to the existing VHDL MIPS model will be required. For a suggested change, see the
3. Write a MIPS test program for the AND, OR, and SUB instructions and run it on the VHDL MIPS simulation. These are all R-format instructions just like the ADD instruction. Modifications to the memory initialization files, program.mif and dmemory.mif, (i.e. only if you use data from memory in the
2. Recompile the MIPS model using the VIDEO_MIPS.VHD file, which generates video output. Download the design to the FPGA board. Attach a VGA monitor to the FPGA board. Single step through the program using the pushbuttons.
1. Use VHDL to synthesize the MIPS single clock cycle design in the file TOP_SPIM.VHD. After synthesis and simulation perform the following steps:Display and print the timing diagram from the simulation. Verify that the information on the timing diagram shows that the hardware is functioning
Robots that detect mines
Robots that collect objects
Fire Fighting Robots
Robot Laser Tag
Robot Soccer Teams
Sumo Wrestling
Robot Dance Contest
Robot Maze Solving
22. Develop and hold a FPGA-bot design contest. Information on previous and current robotics contests can be found online at various web sites. Here are some ideas that have been used for other robot design contests:

Showing 1 - 100 of 426

Rapid Prototyping Of Digital Systems 2nd Edition James O Hamblen, Tyson S Hall, Michael D Furman - Solutions

Step by Step Answers