Questions and Answers of Rapid Prototyping Of Digital Systems

10. A small wire wrap protoboard with holes on .1” centers cut down to 2” by 2.8”. A This is used to make a protoboard for use with the UP3 board. The protoboard contains connectors for servos
9. A 2 to 3 inch strip of .1” single row breakaway headers. DigiKey #S1021-36 or equivalent These headers are used to make custom servo and sensor connectors on the protoboard. They can be soldered
8. Three 40-pin .1-inch double row PC board mount female header sockets, DigiKey#S4310 or equivalent. These sockets are soldered into a small 0.1” center wire wrap protoboard that fits into the
7. A charger for the 7.2V or 8.4V battery pack. An adjustable DC power supply can be used to charge the battery if it is properly adjusted and timed so that the battery is not overcharged.
6. A Castering Wheel or Two small Teflon or Nylon Furniture Slides. There is a bit too much mechanical play in common furniture casters for a small robot and they tend to randomly deflect the robots
5. Two Acroname or Lynxmotion servo wheels. These wheels are 2 ¾ plastic wheels that are designed to attach to the servo’s output shaft spline. Prather Products 2¼-inch aluminum racing wheels
4. Kyosho Female Battery connector with wire leads, Duratrax or Tower Hobbies#DTXC2280. This is used to connect to battery. A connector is needed so that the battery can be disconnected from the
3. Two modified R/C Servomotors. Two identical model servos are required so that the motors run at the same speed. Servo modifications are described in section 13.3. Any servo should work. The
2. A 7.2V to 8.4V 1300-1700mAh Rechargeable NiCAD battery pack with the standard Kyosho battery connector. This is a standard R/C car part, and it is used to power the FPGA-bot. For a small
1. An Altera FPGA Board. The FPGA board serves as the controller for the FPGA-bot. It is attached to the FPGA-bot body with screws. No modifications are required to the board. Any of the Altera FPGA
4. Obtain an IC chip with an SPI or I2 C interface and design an interface for it on the FPGA board. Chips with SPI interfaces include analog-to-digital converters, digital-to-analog converters and
3. Design an I2 C interface for the UP3 board’s real-time clock chip. Display the time from the chip on the UP3 board’s LCD display. Don’t forget to check the UP3 board’s jumper settings and
2. Interface the FPGA board’s serial port (DE1, DE2 or UP3) to a PC serial port using a serial cable. Run a serial communications program on the PC. Send a short message to the PC from the FPGA and
1. Interface a printer with a parallel port to the UP3 board’s parallel port. Connect the two devices using a printer cable. Design logic using a state machine or a processor core for the FPGA to
9. Write a mouse driver in Verilog. Use the mouse information provided in sections 11.2 and 11.3.
8. Use the mouse as an input device in another design with video output or a simple video game such as pong, breakout, or Tetris.
7. Use the mouse as input to a video etch-a-sketch. Use a monochrome 128 by 128 1-bit pixel RAM with the VGA_Sync core in your video design. Display a cursor. To draw a line, the left mouse button
6. Generate a video display that has a moving cursor controlled by the mouse using the Mouse and VGA_Sync FPGAcores. Use the mouse buttons to change the color of the cursor.
5. Use the keyboard as a new input device for a video game, the μP1 computer, or another application.
4. Write the keyboard module in another HDL such as Verilog.
3. Develop a keyboard module that uses the alternate scan code set used by the PC.
2. After reading the section on the PS/2 mouse, design an interface that can also send commands to the keyboard. Demonstrate that the design works correctly by changing the status of the keyboard
1. Write a VHDL module to read a keyboard scan code and display the entire scan code string in hexadecimal on the VGA display using the VGA_SYNC and CHAR_ROM FPGAcores. It will require the use of the
11. Modify the VGA Sync core to support a higher screen resolution and demonstrate it using one of the earlier example video designs.
10. Add color mixing or dithering with more than 8 colors to the previous problem. The 3-bit color code in the RLE encoded memory can be used to map into a color palette. The color palette contains
9. Using Matlab or C, write a program to convert a color bitmap into a *.mif file with runlength encoding. Design a state machine to read out the memory and generate the RGB color signals to display
8. Use the character font ROM and the ideas from the MIPS character output example to add video character output to another complex design.
7. Design your own video game with graphics. Some ideas include breakout, space invaders, Tetris, a slot machine, poker, craps, blackjack, pinball, and roulette. Keep the ?
6. Make a Pong-type video game by using pushbutton input to move a paddle up and down that the ball will bounce off of.
5. Draw a more detailed ball in the bouncing ball example. Use a small ROM to hold a small detailed color image of a ball.
4. Modify the example to support different speeds. Read the speed of the ball from the FPGA switches.
3. Modify the bouncing ball example to move up or down based on input from the two pushbuttons.
2. Modify the bouncing ball example to bounce and move in both the X and Y directions.You will need to add code for motion in two directions and check additional walls for a bounce condition.
1. Design a video output display that displays a large version of your initials. Hint: use the character generation ROM, the Video Sync FPGAcore, and some of the higher bits of the row and column
17. Use the implementation approach in the μP 3 computer model as a starting point to implement the basic instruction set of a different computer from your digital logic textbook or other reference
16. Using the two low-bits from the opcode field, add a register address field that selects one of four different data registers A, B, C, or D for each instruction.
15. Add all of the instructions and features suggested in the exercises to the μP 3 computer and use it as a microcontroller core for one of the robot projects suggested in Chapter 12.Additional
14. Implement a stack as suggested in the previous problem and add instructions to PUSH or POP register AC from the stack. At reset, set the stack pointer to the highest address of data memory.
13. Add a subroutine CALL and RETURN instruction to the μP 3 computer design. Use a dedicated register to store the return address or use a stack with a stack pointer register.The stack should start
12. Modify the μP 3 computer so that it uses two different memories. Use one memory for instructions and a new memory for data values. The new data memory should be 256 or 512 (see previous problem
11. Expand the memory address space of the μP 3 computer from eight bits to nine bits.Some registers will also need an additional bit. Use 512 locations of 16-bit memory.Expand the address field by
10. Add the WAIT instruction to the simple computer model and verify with a test program and simulation. WAIT value, loads and starts an 8-bit ten-millisecond (10-2 second) timer and then waits
9. Add video character output and keyboard input to the computer, after studying the material presented in Chapters 9 and 10.
8. Modify the video output display described in Chapter 9 for the MIPS computer example to display the μP 3’s internal registers. While running on the FPGA board, use the pushbuttons for clock and
7. Use the timing analyzer to determine the maximum clock rate for the μP 3 computer.Using this value, compute the execution time for the example program in Figure 9.4.
6. Add these two input/output (I/O) instructions to the μP 3 computer model running on the UP3 board.
5. Run the μP 3 computer model using one of the FPGA boards. Use a debounced pushbutton for the clock and the other pushbutton for reset. Output the PC in hex to the LCD display or seven segment
4. Add the following two shift instructions to the simple computer model and verify with a test program and simulation.
3. Add the instructions in the table below to the VHDL model, construct a test program for each instruction, compile and simulate to verify correct operation. In JPOS and JZERO instructions, both
2. Add the JNEG execute state to the CASE statement in the model. JNEG is Jump if AC = 0 the next sequential instruction is executed. In most cases, a new instruction will just require a new execute
1. Compile and simulate the μP 3 computer VHDL or Verilog model. Rewrite the machine language program in the program.mif file to compute A = (B + C) + D. Store D in location 13 in memory. End the
5. Implement a real train setup using DCC model trains. Debug your control module using the video simulation module first, to avoid any real train crashes that may damage the trains. Typically
4. Develop another pattern of train movement and design a state machine to implement it.
3. Use the single pulse FPGAcore functions on each raw sensor input to produce state machine sensor inputs that go High for only one clock cycle per passage of a train.Rework the state machine design
2. Design a state machine to operate the two trains avoiding collisions but minimizing their idle time. Trains must not crash by moving the wrong direction into an open switch.Develop a simulation to
1. Assuming that train A now runs clockwise and B remains counterclockwise, draw a new state diagram and implement the new controller. If you use VHDL to design the new controller, you can modify the
7. Implement a 128 by 32 RAM using Verilog and the Altsyncram function. Do not use registered output options. Target the design to the Cyclone II device. Use the timing analysis tools to determine
6. Replace the 8count block used in the tutorial in Chapter 4, with a new counter module written in Verilog. Simulate the design and download a test program to the UP3 board.
5. Develop a Verilog model of one of the TTL chips listed below. The model should be functionally equivalent, but there will be timing differences. Compare the timing differences between the Verilog
4. Explore different synthesis options for the ALU from problem 3. Change the area and speed synthesis settings in the compiler under Assignments DSettings DAnalysis and Synthesis Settings, rerun the
3. Use the Cyclone chip as the target device. Determine the worst case time delay of the ALU using the timing analyzer. Examine the report file and find the device utilization.Use the logic element
2. Write a Verilog model for a 32-bit, arithmetic logic unit (ALU). Verify correct operation with a simulation using the Altera CAD tools. A and B are 32-bit inputs to the ALU, and Y is the output. A
1. Write a Verilog model for the state machine shown in the following state diagram and verify correct operation with a simulation using the Altera CAD tools. A and B are the two states, X is the
9. Study the VHDL code in the LCD Display FPGAcore function and draw a state diagram of the initialization and data transfer operations and explain its operation. You may find it helpful to examine
8. Implement a 128 by 32 RAM using VHDL and the Altsyncram function. Do not use registered output options. Target the design to the Cyclone EP1C6240C8 device. Use the timing analyzer to determine the
7. Replace the 8count block used in the tutorial in Chapter 4, with a new counter module written in VHDL. Simulate the design and download a test program to the UP3 board.
6. Develop a VHDL model of one of the TTL chips listed below. The model should be functionally equivalent, but there will be timing differences. Compare the timing differences between the VHDL FPGA
5. Explore different synthesis options for the ALU from problem 3. Change the area and speed synthesis settings in the compiler under Assignments DSettings DAnalysis and Synthesis Settings, rerun the
4. Use the Cyclone chip as the target device. Determine the worst case time delay of the ALU using the timing analyzer. Examine the report file and find the device utilization.Use the logic element
3. Write a VHDL model for a 32-bit, arithmetic logic unit (ALU). Verify correct operation with a simulation using the Altera CAD tools. A and B are 32-bit inputs to the ALU, and Y is the output. A
2. Write a VHDL model for the state machine shown in the following state diagram and verify correct operation with a simulation using the Altera CAD tools. A and B are the two states, X is the
1. Rewrite and compile the VHDL model for the seven-segment decoder in Section 6.5 replacing the PROCESS and CASE statements with a WITH…SELECT statement.
9. For a more challenging problem, port the eCos operating system to a DE Board. It is available free at www.niosforum.com. First, run a simple hello world application using the UART. For the second
7. Obtain the licenses needed for the MicroC/OS-II Nios II OS port. The license for the Nios II MicroC/OS-II port is available from Micrium (www.micrium.com) and a full commercial license for the
6. Create a new HTML page on your PC and save it to a USB flash drive. Insert the drive into the USB slot on the DE2 board. Mount the drive as discussed in the chapter. Delete the
5. Using the ps, kill, and free commands, try stopping and starting the dhcdcd, inetd, telnetd, ftpd, and boa programs one at a time. Record the approximate memory required for each program to run.
4. Using the ps, kill, and free commands, try stopping and starting the nano-X, nanowm, and other graphical programs one at a time. Record the approximate memory required for each program to run.
3. Follow the instructions in the chapter for establishing a network connection on the DE2 board and starting the boa web server. To demonstrate the working system, open a web browser on your PC and
2. Load a small (~20KB) JPEG image onto a USB flash drive. Insert the drive into the USB slot on the DE2 board. Mount the drive as discussed in the chapter and use the nxview program to display the
1. In Figure 18.4, notice that the clock frequency is set to 100 MHz. To handle the computational needs of an operating systems, the clock rate was increased from the 50 MHz clock used in Chapter 17.
13. Program a complete Nios II design into both Flash memories so that the FPGA board loads both the FPGA hardware configuration data and the software from the two Flash memories automatically at
12. Program the FPGA’s serial flash device so that your Nios II hardware design loads automatically at power up. See Appendix E for instructions on programming the FPGA’s serial flash
11. Interface the dual port video display memory used in one of the earlier problems directly to the Avalon system bus instead of using PIO ports. See the Avalon Interface Specification Manual.
10. Add a custom instruction to the Nios II processor designed to speed up a particular application area. See the Nios II Custom Instruction User Guide. Demostrate the speedup obtained with the new
9. After solving the previous two problems, develop software for a video game that uses the mouse or keyboard for input and displays output on the monitor. If you need graphics for your game,
8. Use the video sync core and character generation ROM from Chapter 10 to add a video text display to the Nios processor. Add a dual port memory to store a screen full of characters. Write charcters
7. Interface a PS/2 keyboard or mouse to the Nios II processor using PIO ports. Write software to demonstrate the new keyboard or mouse interface. Display the output on the LCD or the UART. There are
6. Design an automatic setback HVAC thermostat using the FPGA. Interface a temperature sensor to the FPGA. Some temperature sensors are available with digital outputs that would not require a
5. Implement one of the FPGA robotics projects from Chapter 13 using a Nios II processor running C code. See problem 1 for robot interface suggestions.
4. Add an SPI interface to the Nios II hardware design and use it to interface to an external SPI device connected to one of the FPGA board’s expansion connectors.
3. Add a parallel port to the Nios II hardware design. Use two 8-bit ports, one for data and one for status and control bits. Connect the PIO port’s I/O bits to the parallel port connector on the
2. Add a PIO port to the Nios II hardware design and use the PIO port’s I/O bits to design an I2 C hardware interface to the FPGA board’s real-time clock chip. Software will be needed to send I2
1. Add two 8-bit PIOs to the Nios II hardware design that connect to the 5 volt I/O pins on the board’s header connector. Setup one port for input and one port for output. Connect the PIO port’s
Specify the top-level pin assignments and project settings necessary for implementing the Nios processor on the DE boards.
Create a PLL that supplies a clock signal for the on-board SDRAM, and
Generate a custom Nios II processor core,
Navigate Altera’s SOPC Builder (Nios II processor design wizard),
6. Port an interesting C application program to the Nios II processor. Execute the application from SDRAM.
5. Write a retro version of the 1970’s classic kill the bit computer game for the DE board.The goal in the kill the bit game is to turn off all of the four LEDs using the four pushbuttons. The game
4. Memory test programs cannot test all possible patterns. Research the various algorithms widely used in more thorough memory test programs and write your own more advanced memory test program for

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