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rapid prototyping of digital systems

Questions and Answers of Rapid Prototyping Of Digital Systems

6. Make a Pong-type video game by using pushbutton input to move a paddle up and down that the ball will bounce off of.
5. Draw a more detailed ball in the bouncing ball example. Use a small ROM to hold a small detailed color image of a ball.
4. Modify the example to support different speeds. Read the speed of the ball from the FPGA switches.
3. Modify the bouncing ball example to move up or down based on input from the two pushbuttons.
2. Modify the bouncing ball example to bounce and move in both the X and Y directions.You will need to add code for motion in two directions and check additional walls for a bounce condition.
1. Design a video output display that displays a large version of your initials. Hint: use the character generation ROM, the Video Sync FPGAcore, and some of the higher bits of the row and column
17. Use the implementation approach in the μP 3 computer model as a starting point to implement the basic instruction set of a different computer from your digital logic textbook or other reference
16. Using the two low-bits from the opcode field, add a register address field that selects one of four different data registers A, B, C, or D for each instruction.
15. Add all of the instructions and features suggested in the exercises to the μP 3 computer and use it as a microcontroller core for one of the robot projects suggested in Chapter 12.Additional
14. Implement a stack as suggested in the previous problem and add instructions to PUSH or POP register AC from the stack. At reset, set the stack pointer to the highest address of data memory.
13. Add a subroutine CALL and RETURN instruction to the μP 3 computer design. Use a dedicated register to store the return address or use a stack with a stack pointer register.The stack should start
12. Modify the μP 3 computer so that it uses two different memories. Use one memory for instructions and a new memory for data values. The new data memory should be 256 or 512 (see previous problem
11. Expand the memory address space of the μP 3 computer from eight bits to nine bits.Some registers will also need an additional bit. Use 512 locations of 16-bit memory.Expand the address field by
10. Add the WAIT instruction to the simple computer model and verify with a test program and simulation. WAIT value, loads and starts an 8-bit ten-millisecond (10-2 second) timer and then waits
9. Add video character output and keyboard input to the computer, after studying the material presented in Chapters 9 and 10.
8. Modify the video output display described in Chapter 9 for the MIPS computer example to display the μP 3’s internal registers. While running on the FPGA board, use the pushbuttons for clock and
7. Use the timing analyzer to determine the maximum clock rate for the μP 3 computer.Using this value, compute the execution time for the example program in Figure 9.4.
6. Add these two input/output (I/O) instructions to the μP 3 computer model running on the UP3 board.
5. Run the μP 3 computer model using one of the FPGA boards. Use a debounced pushbutton for the clock and the other pushbutton for reset. Output the PC in hex to the LCD display or seven segment
4. Add the following two shift instructions to the simple computer model and verify with a test program and simulation.
3. Add the instructions in the table below to the VHDL model, construct a test program for each instruction, compile and simulate to verify correct operation. In JPOS and JZERO instructions, both
2. Add the JNEG execute state to the CASE statement in the model. JNEG is Jump if AC = 0 the next sequential instruction is executed. In most cases, a new instruction will just require a new execute
1. Compile and simulate the μP 3 computer VHDL or Verilog model. Rewrite the machine language program in the program.mif file to compute A = (B + C) + D. Store D in location 13 in memory. End the
5. Implement a real train setup using DCC model trains. Debug your control module using the video simulation module first, to avoid any real train crashes that may damage the trains. Typically
4. Develop another pattern of train movement and design a state machine to implement it.
3. Use the single pulse FPGAcore functions on each raw sensor input to produce state machine sensor inputs that go High for only one clock cycle per passage of a train.Rework the state machine design
2. Design a state machine to operate the two trains avoiding collisions but minimizing their idle time. Trains must not crash by moving the wrong direction into an open switch.Develop a simulation to
1. Assuming that train A now runs clockwise and B remains counterclockwise, draw a new state diagram and implement the new controller. If you use VHDL to design the new controller, you can modify the
7. Implement a 128 by 32 RAM using Verilog and the Altsyncram function. Do not use registered output options. Target the design to the Cyclone II device. Use the timing analysis tools to determine
6. Replace the 8count block used in the tutorial in Chapter 4, with a new counter module written in Verilog. Simulate the design and download a test program to the UP3 board.
5. Develop a Verilog model of one of the TTL chips listed below. The model should be functionally equivalent, but there will be timing differences. Compare the timing differences between the Verilog
4. Explore different synthesis options for the ALU from problem 3. Change the area and speed synthesis settings in the compiler under Assignments DSettings DAnalysis and Synthesis Settings, rerun the
3. Use the Cyclone chip as the target device. Determine the worst case time delay of the ALU using the timing analyzer. Examine the report file and find the device utilization.Use the logic element
2. Write a Verilog model for a 32-bit, arithmetic logic unit (ALU). Verify correct operation with a simulation using the Altera CAD tools. A and B are 32-bit inputs to the ALU, and Y is the output. A
1. Write a Verilog model for the state machine shown in the following state diagram and verify correct operation with a simulation using the Altera CAD tools. A and B are the two states, X is the
9. Study the VHDL code in the LCD Display FPGAcore function and draw a state diagram of the initialization and data transfer operations and explain its operation. You may find it helpful to examine
8. Implement a 128 by 32 RAM using VHDL and the Altsyncram function. Do not use registered output options. Target the design to the Cyclone EP1C6240C8 device. Use the timing analyzer to determine the
7. Replace the 8count block used in the tutorial in Chapter 4, with a new counter module written in VHDL. Simulate the design and download a test program to the UP3 board.
6. Develop a VHDL model of one of the TTL chips listed below. The model should be functionally equivalent, but there will be timing differences. Compare the timing differences between the VHDL FPGA
5. Explore different synthesis options for the ALU from problem 3. Change the area and speed synthesis settings in the compiler under Assignments DSettings DAnalysis and Synthesis Settings, rerun the
4. Use the Cyclone chip as the target device. Determine the worst case time delay of the ALU using the timing analyzer. Examine the report file and find the device utilization.Use the logic element
3. Write a VHDL model for a 32-bit, arithmetic logic unit (ALU). Verify correct operation with a simulation using the Altera CAD tools. A and B are 32-bit inputs to the ALU, and Y is the output. A
2. Write a VHDL model for the state machine shown in the following state diagram and verify correct operation with a simulation using the Altera CAD tools. A and B are the two states, X is the
1. Rewrite and compile the VHDL model for the seven-segment decoder in Section 6.5 replacing the PROCESS and CASE statements with a WITH…SELECT statement.
1. The tutorials ORed the active low signals from the pushbuttons and produced an output that was required to be low to turn off an LED. This was accomplished with the"negative-logic OR" gate
2. Substitute in the VHDL code:LED
3. Design a logic circuit to turn on the LED when both pushbuttons are pressed. Compile, simulate, and download the new circuit.
4. Try a different logic function such as XOR. Start at the beginning or edit your existing schematic by deleting and replacing the BNOR2 symbol. Next repeat the tutorial steps to compile, simulate,
5. Repeat problem 2 for all of the basic gates including, OR, NOR, NAND, XOR, XNOR, and NOT. Try using different LEDs and output your results simultaneously. Look up the pin connections for the FPGA
6. Design, enter, simulate and implement a more complex logic gate network. One suggestion is a half adder. You will need two LED outputs.
7. In the schematic editor, try building the design with some 74xx TTL parts from the others maxplus2 symbol library.
8. Draw a schematic and develop a simulation to test the 2-to-1 Mux function in the others maxplus2 symbol library.
9. View the orgate.rpt file and find the device utilization, the pin assignments, and the netlist. A substantial portion of the time delay in this simple logic design is the input and output buffer
10. Use the chip editor to move the logic cell used in the OR-gate design to another location inside the FPGA. For information of the chip editor, use the Quartus II Help function.Try moving the LE
11. Remove the pin number constraints from the schematic and let the compiler assign the pin locations. Rerun the timing analyzer and compare the time delays. Are they faster or slower than having
12. If you are using a UP2 board, retarget the example design to the MAX chip. Pin numbers for the MAX decimal point LED can be found in the UP2 User manual. It will be necessary to connect jumper
13. If a storage oscilloscope or a fast logic analyzer is available, compare the predicted delay times from the simulation and timing analysis to the actual delays measured on the FPGA board. Force
14. Draw a schematic that uses the LPM_ADD_SUB megafunction to add two signed numbers on the Cyclone device. Use Tools D Megawizard to start the megawizard to help configure LPM symbols. Verify the
15. Use the DFF part from the primitives storage library and enter the symbol in a schematic using the graphical editor. Develop a simulation that exercises all of the features of the D flip-flop.
16. Use the DFFE part from the primitives storage library and enter the symbol in a schematic using the graphical editor. Develop a simulation that exercises all of the features of the D flip-flop
17. Use gates and a DFF part from the primitives storage library with graphical entry to implement the state machine shown in the following state diagram. Verify correct operation with a simulation
18. Repeat the previous problem but use one-hot encoding on the state machine. For one-hot encoding use two flip-flops with only one active for each state. For state A the flip-flop outputs would be
1. Show how the logic equation (A AND NOT(B)) OR (C AND NOT(D)) can be implemented using the following:A. The PLA in Figure 3.3 B. The LUT in Figure 3.9 Be sure to include the PLA fuse pattern and
2. Examine the compiler report file and use the chip editor to explain how the OR-gate design in the tutorial in Chapter 1 was mapped into the Cyclone device.
3. Retarget the design from Chapter 1 to a MAX 7000S device. Examine the compiler report file and use the chip editor to explain how the OR-gate design in the tutorial in Chapter 1 was mapped into
4. Show how the logic equation (A AND NOT(B)) OR (C AND NOT(D)) can be implemented in the following:A. A MAX Logic Element B. A Cyclone Logic Element C. An XC4000 CLB Be sure to include the contents
5. Using data sheets available on the web, compare and contrast the features of newer generation FPGAs such as Altera’s Cyclone III and Stratix III, and Xilinx’s Virtex II and Virtex 4 families.
Understand the fundamentals of hierarchical design tools,
Complete an example of a sequential logic design,
Use the FPGAcore library designed for the FPGA boards,
Use a hex display, pushbuttons, and the onboard clock,
Use buses in a schematic, and
Be able to perform automatic timing analysis of sequential circuits.
1. Simulate the initial design without the switch debounce circuit by setting up an initial reset pulse and a periodic 200 ns clock input in the simulator. In sequential simulations, turn on the
2. Modify the counter circuit so that it counts down or up depending on the state of a switch input. See Table 2.4 for the pin assignment for the new switch input.
3. Modify the counter circuit so that it parallel loads a count value from the four switches on the FPGA board when PB2 is pushed. Zero out the low four counter bits during a load.Since the switch
4. Build a stopwatch with the following modifications to the design. Disconnect the counter clk line and connect it to the clock_10hz pin on the clock_div symbol. Clock a toggle flip-flop with the
5. The elapsed time in the stopwatch from problem 3 is displayed in hexadecimal. Replace the counter with two cascaded binary-coded-decimal (BCD) counters so that it displays the elapsed time as two
6. Build a watch by expanding the counter circuit to count seconds, hours, and minutes. The two pushbuttons reset and start the watch.
7. Replace the lpm_counter0 logic with a VHDL or Verilog counter design, simulate the design, and verify operation on the FPGA board. Read Chapter 5 and note the example counter design in section
8. Draw a schematic, develop a simulation, and download a design to the FPGA board that uses the LCD displays for outputs and the DIP switch for input, to test the 74161 4-bit TTL counter function
9. Draw a schematic, develop a simulation, and download a design to the FPGA board to test the following functions that can be created with the MegaWizard:LPM_ADD_SUB: a 2-bit adder/subtractor; test
10. Draw a schematic and develop a simulation to test the LPM_ROM megafunction. Create a sixteen word ROM with eight data bits per word. Specify initial values in hex for the ROM in a memory
11. Using gates and the DFF part from the primitives/storage library, design a circuit that implements the state machine shown below. Use two D flip-flops with an encoded state.
12. Repeat the previous problem using one-hot encoding. Recall that one-hot encoding uses one flip-flop per state, and only one flip-flop is ever active at any given time in valid states. The state

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