5. Develop a Verilog model of one of the TTL chips listed below. The model should be functionally equivalent, but there will be timing differences. Compare the timing differences between the Verilog FPGA implementation and the TTL chip. Use a data book or find a data sheet using the World Wide Web.

F. 7400 Quad nand gate G. 74LS241 Octal buffer with tri-state output H. 74LS273 Octal D flip-flop with Clear I. 74163 4-bit binary counter J. 74LS181 4-bit ALU