1. In Figure 18.4, notice that the clock frequency is set to 100 MHz. To handle the computational needs of an operating systems, the clock rate was increased from the 50 MHz clock used in Chapter 17. Changing the clock frequency required several changes in the PLL settings that generate the processor and memory clocks. Open the Quartus II project for Chapter 18 that is provided on the DVD. What are the frequencies of the three clock signals being generated by the PLL block? Why is the phase shift of the SDRAM clock set to 108 degrees instead of the 54 degrees specified in Chapter 17?