(a) Design an NMOS depletion-load logic gate that implements the function \(\bar{Y}=[A+B \cdot(C+D)]\).

(b) Assume \(V_{D D}=2.5 \mathrm{~V},(W / L)_{L}=1\), \(V_{T N D}=0.4 \mathrm{~V}\), and \(V_{T N L}=-0.6 \mathrm{~V}\). Determine \((W / L)_{D}\) of each transistor such that \(V_{O L}(\max )=50 \mathrm{mV}\).