The Boolean function for a carry-out signal of a one-bit full adder is given by

\[\text { Carry-out }=A \cdot B+A \cdot C+B \cdot C\]

(a) Design an NMOS logic circuit with depletion load to perform this function. Signals \(A, B\), and \(C\) are available.

(b) Assume \((W / L)_{L}=1\), \(V_{D D}=5 \mathrm{~V}, V_{T N L}=-1.5 \mathrm{~V}\), and \(V_{T N D}=0.8 \mathrm{~V}\). Determine the \(W / L\) ratio of the other transistors such that the maximum logic 0 value in any part of the circuit is \(0.2 \mathrm{~V}\).