Consider the input stage and bias circuit of the 741 op-amp shown in Figure 13.5. Design a complementary circuit such that the input transistors are pnp devices, and the bias currents are \(I_{\text {REF }}=0.4 \mathrm{~mA}\) and \(I_{C 10}=24 \mu \mathrm{A}\) when the circuit is biased at \(\pm 5 \mathrm{~V}\).

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Noninverting input Q8 Inverting input 12 Q2 Rs= 40 Q3 Q4 Offset Q5 null ww R => 1 Q7 300 www R3 = 50 Q6 ww R = 1 210 IREF R4= 15 Offset Input stage null Bias circuit V+ V- Figure 13.5 Bias circuit and input stage portion of 741 op-amp circuit