The circuit shown in Figure P10.52 is biased at \(V^{+}=+2 \mathrm{~V}\) and \(V^{-}=\) \(-2 \mathrm{~V}\). Assume the transistor parameters are \(V_{T P}=-0.35 \mathrm{~V}, k_{p}^{\prime}=\) \(50 \mu \mathrm{A} / \mathrm{V}^{2}\), and \(\lambda=0\). Design the circuit such that \(I_{\mathrm{REF}}=200 \mu \mathrm{A}\), \(I_{O}=100 \mu \mathrm{A}\), and \(V_{S D 2}(\mathrm{sat})=1.2 \mathrm{~V}\).

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IREF V+ M M M3 Figure P10.52 10