The transistor circuit shown in Figure P10.54 is biased at \(V^{+}=+5 \mathrm{~V}\) and \(V^{-}=-5 \mathrm{~V}\). The transistor parameters are \(V_{T P}=-1.2 \mathrm{~V}, k_{p}^{\prime}=\) \(80 \mu \mathrm{A} / \mathrm{V}^{2}, \lambda=0,(W / L)_{1}=(W / L)_{2}=25\), and \((W / L)_{3}=(W / L)_{4}=4\). Determine \(I_{\mathrm{REF}}, I_{O}\), and \(V_{S D 2}(\mathrm{sat})\).

Transcribed Image Text:

Mi M2 IREF M3 M4 Figure P10.54 1o