The CMOS folded cascode amplifier of Figure 13.17 is to be designed to provide a differential voltage gain of 25,000 . The maximum power dissipated in the circuit is to be limited to \(3 \mathrm{~mW}\). Assume transistor parameters as described in Problem 13.43, except the relation between NMOS and PMOS width-to-length ratios need not be maintained.

Data From Problem 13.43:-

The CMOS folded cascode amplifier in Figure 13.17 is to be redesigned to provide a differential voltage gain of 10,000 . The biasing is the same as described in Problem 13.42. The transistor parameters are \(V_{T N}=0.5 \mathrm{~V}\), \(V_{T P}=-0.5 \mathrm{~V}, k_{n}^{\prime}=80 \mu \mathrm{A} / \mathrm{V}^{2}, k_{p}^{\prime}=35 \mu \mathrm{A} / \mathrm{V}^{2}, \lambda_{n}=0.015 \mathrm{~V}^{-1}\), and \(\lambda_{p}=0.02 \mathrm{~V}^{-1}\). Assume \((W / L)_{p}=2.2(W / L)_{n}\) where appropriate so that the electrical parameters of PMOS and NMOS devices are nearly identical.

Data From Problem 13.42:-

The CMOS folded cascode circuit in Figure 13.17 is biased at \(\pm 5 \mathrm{~V}\) and the reference current is \(I_{\mathrm{REF}}=50 \mu \mathrm{A}\). The transistor parameters are \(V_{T N}=0.5 \mathrm{~V}, V_{T P}=-0.5 \mathrm{~V}, K_{n}=K_{p}=0.5 \mathrm{~mA} / \mathrm{V}^{2}\), and \(\lambda_{n}=\lambda_{p}=\) \(0.015 \mathrm{~V}^{-1}\).

(a) Determine the small-signal differential voltage gain.

(b) Find the output resistance of the circuit.

(c) If the capacitance at the output node is \(C_{L}=5 \mathrm{pF}\), determine the unity-gain bandwidth of the amplifier.

Transcribed Image Text:

M11 M12 JREF 22 M13 M2 vd i=8m2 vd | i=8m Mo M10 M Mg Vo VB2 Rob M6 M5 MA M3 Figure 13.17 CMOS folded cascode amplifier