The multitransistor circuit in Figure 5.61 is to be redesigned. The bias voltages are to be \(\pm 3.3\mathrm{~V}\) and the nominal transistor current gains are \(\beta=120\). Design a bias-stable circuit such that \(I_{C Q 1}=100 \mu \mathrm{A}, I_{C Q 2}=200 \mu \mathrm{A}\), and \(V_{C E Q 1} \cong V_{E C Q 2} \cong 3 \mathrm{~V}\)

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+5 V RC = 5kQ RE2 = 2 k R = 100 k Q2 R2 = 50 Rc2 = 1.5 k RE1 = 2 k -5 V Figure 5.61 A multistage transistor circuit